bdb2629d63
for the '40. Support for more scsi controllers (zeus, magnum) Support for more tapes (in st.c) New custom chip console code integrated.
175 lines
4.9 KiB
C++
175 lines
4.9 KiB
C++
/*
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* Copyright (c) 1982, 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)if_lereg.h 7.1 (Berkeley) 5/8/90
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* $Id: if_lereg.h,v 1.3 1994/01/26 21:05:53 mw Exp $
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*/
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#define LEID 21
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#define LEMTU 1518
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#define LEMINSIZE 60 /* should be 64 if mode DTCR is set */
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/* HP seems to have 16K RAM on board, A2065/Ameristar come with 32K.
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First try to get a working driver with the HP values, and later
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try and see whether 32K works too. */
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#define LE_USE_16K
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#ifdef LE_USE_16K
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#define LERBUF 8
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#define LERBUFLOG2 3
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#define LETBUF 1
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#define LETBUFLOG2 0
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#else /* 32K */
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#define LERBUF 16
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#define LERBUFLOG2 4
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#define LETBUF 2
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#define LETBUFLOG2 1
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#endif
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#define LE_RLEN (LERBUFLOG2 << 13)
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#define LE_TLEN (LETBUFLOG2 << 13)
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#define vu_char volatile u_char
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/*
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* LANCE registers.
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*/
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#if 0
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/* doesn't exist on amiga, there's autoconfig registers in this area */
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struct lereg0 {
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u_char ler0_pad0;
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vu_char ler0_id; /* ID */
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u_char ler0_pad1;
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vu_char ler0_status; /* interrupt enable/status */
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};
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#endif
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struct lereg1 {
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u_short ler1_rdp; /* data port */
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u_short ler1_rap; /* register select port */
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};
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/*
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* Overlayed on 16K dual-port RAM.
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* Current size is 13,758 bytes with 8 x 1518 receive buffers and
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* 1 x 1518 transmit buffer.
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*/
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struct lereg2 {
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/* init block */
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u_short ler2_mode; /* +0x0000 */
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u_char ler2_padr[6]; /* +0x0002 */
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u_long ler2_ladrf0; /* +0x0008 */
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u_long ler2_ladrf1; /* +0x000C */
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u_short ler2_rdra; /* +0x0010 */
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u_short ler2_rlen; /* +0x0012 */
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u_short ler2_tdra; /* +0x0014 */
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u_short ler2_tlen; /* +0x0016 */
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/* receive message descriptors */
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struct lermd { /* +0x0018 */
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u_short rmd0;
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u_short rmd1;
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short rmd2;
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u_short rmd3;
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} ler2_rmd[LERBUF];
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/* transmit message descriptors */
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struct letmd { /* +0x0058 */
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u_short tmd0;
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u_short tmd1;
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short tmd2;
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u_short tmd3;
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} ler2_tmd[LETBUF];
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char ler2_rbuf[LERBUF][LEMTU]; /* +0x0060 */
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char ler2_tbuf[LETBUF][LEMTU]; /* +0x2FD0 */
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};
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#if 0
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/*
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* Control and status bits -- lereg0
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*/
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#define LE_IE 0x80 /* interrupt enable */
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#define LE_IR 0x40 /* interrupt requested */
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#define LE_LOCK 0x08 /* lock status register */
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#define LE_ACK 0x04 /* ack of lock */
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#define LE_JAB 0x02 /* loss of tx clock (???) */
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#define LE_IPL(x) ((((x) >> 4) & 0x3) + 3)
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#endif
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/*
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* Control and status bits -- lereg1
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*/
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#define LE_CSR0 0
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#define LE_CSR1 1
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#define LE_CSR2 2
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#define LE_CSR3 3
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#define LE_SERR 0x8000
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#define LE_BABL 0x4000
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#define LE_CERR 0x2000
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#define LE_MISS 0x1000
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#define LE_MERR 0x0800
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#define LE_RINT 0x0400
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#define LE_TINT 0x0200
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#define LE_IDON 0x0100
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#define LE_INTR 0x0080
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#define LE_INEA 0x0040
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#define LE_RXON 0x0020
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#define LE_TXON 0x0010
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#define LE_TDMD 0x0008
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#define LE_STOP 0x0004
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#define LE_STRT 0x0002
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#define LE_INIT 0x0001
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#define LE_BSWP 0x4
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#define LE_MODE 0x0
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/*
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* Control and status bits -- lereg2
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*/
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#define LE_OWN 0x8000
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#define LE_ERR 0x4000
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#define LE_STP 0x0200
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#define LE_ENP 0x0100
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#define LE_FRAM 0x2000
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#define LE_OFLO 0x1000
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#define LE_CRC 0x0800
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#define LE_RBUFF 0x0400
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#define LE_MORE 0x1000
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#define LE_ONE 0x0800
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#define LE_DEF 0x0400
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#define LE_TBUFF 0x8000
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#define LE_UFLO 0x4000
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#define LE_LCOL 0x1000
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#define LE_LCAR 0x0800
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#define LE_RTRY 0x0400
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