scw c22fb1db55 Finally nobble the bus_dmamap_sync() problem with osiop(4).
Basically, bus_dmamap_sync() `PREREAD' needs to flush the cache
for the start and end of the region if it is not aligned to
a cacheline boundary, otherwise a subsequent POSTREAD can *purge*
valid data which was in the cacheline but *outside* the region
passed to bus_dmamap_sync().

Bus snooping doesn't always help here because osiop(4) calls
bus_dmamap_sync() with POSTREAD even if no data was actually
transferred! (And we can't rely on snooping on the 68060 models anyway).
2001-05-16 19:06:46 +00:00
2001-05-15 23:50:36 +00:00
2001-05-15 16:00:32 +00:00
2001-05-16 11:51:16 +00:00
2001-05-16 10:45:36 +00:00
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