Finally nobble the bus_dmamap_sync() problem with osiop(4).
Basically, bus_dmamap_sync() `PREREAD' needs to flush the cache for the start and end of the region if it is not aligned to a cacheline boundary, otherwise a subsequent POSTREAD can *purge* valid data which was in the cacheline but *outside* the region passed to bus_dmamap_sync(). Bus snooping doesn't always help here because osiop(4) calls bus_dmamap_sync() with POSTREAD even if no data was actually transferred! (And we can't rely on snooping on the 68060 models anyway).
This commit is contained in:
scw
parent
35f2b9136a
commit
c22fb1db55
@ -1,4 +1,4 @@
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/* $NetBSD: bus_dma.h,v 1.7 2001/03/07 22:42:19 thorpej Exp $ */
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/* $NetBSD: bus_dma.h,v 1.8 2001/05/16 19:06:46 scw Exp $ */
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/*
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* This file was extracted from from next68k/include/bus.h
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@ -123,7 +123,7 @@ struct mvme68k_bus_dma_segment {
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/* PRIVATE */
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bus_addr_t _ds_cpuaddr; /* CPU-relative phys addr of segment */
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int _ds_padding;
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int _ds_flags;
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};
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typedef struct mvme68k_bus_dma_segment bus_dma_segment_t;
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.h,v 1.20 2001/04/22 23:19:28 thorpej Exp $ */
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/* $NetBSD: pmap.h,v 1.21 2001/05/16 19:06:46 scw Exp $ */
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/*
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* Copyright (c) 1987 Carnegie-Mellon University
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@ -135,6 +135,7 @@ extern struct pmap kernel_pmap_store;
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extern void _pmap_set_page_cacheable __P((struct pmap *, vaddr_t));
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extern void _pmap_set_page_cacheinhibit __P((struct pmap *, vaddr_t));
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extern int _pmap_page_is_cacheable __P((struct pmap *, vaddr_t));
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extern struct pv_entry *pv_table; /* array of entries, one per page */
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@ -1,4 +1,4 @@
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/* $NetBSD: bus_dma.c,v 1.13 2001/05/11 13:01:44 scw Exp $ */
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/* $NetBSD: bus_dma.c,v 1.14 2001/05/16 19:06:47 scw Exp $ */
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/*
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* This file was taken from from next68k/dev/bus_dma.c, which was originally
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@ -46,7 +46,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.13 2001/05/11 13:01:44 scw Exp $");
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__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.14 2001/05/16 19:06:47 scw Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -71,12 +71,6 @@ int _bus_dmamap_load_buffer_direct_common __P((bus_dma_tag_t,
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bus_dmamap_t, void *, bus_size_t, struct proc *, int,
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paddr_t *, int *, int));
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/*
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* Initialised in mvme68k/machdep.c according to the host cpu type
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*/
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void (*_bus_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
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bus_size_t, int);
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/*
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* Common function for DMA map creation. May be called by bus-specific
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* DMA map creation functions.
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@ -162,7 +156,7 @@ _bus_dmamap_load_buffer_direct_common(t, map, buf, buflen, p, flags,
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bus_size_t sgsize;
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bus_addr_t curaddr, lastaddr, baddr, bmask;
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vaddr_t vaddr = (vaddr_t)buf;
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int seg;
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int seg, cacheable, coherent = BUS_DMA_COHERENT;
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lastaddr = *lastaddrp;
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bmask = ~(map->_dm_boundary - 1);
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@ -171,11 +165,20 @@ _bus_dmamap_load_buffer_direct_common(t, map, buf, buflen, p, flags,
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/*
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* Get the physical address for this segment.
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*/
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if (p != NULL)
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if (p != NULL) {
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(void) pmap_extract(p->p_vmspace->vm_map.pmap,
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vaddr, &curaddr);
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else
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cacheable =
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_pmap_page_is_cacheable(p->p_vmspace->vm_map.pmap,
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vaddr);
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} else {
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(void) pmap_extract(pmap_kernel(),vaddr, &curaddr);
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cacheable =
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_pmap_page_is_cacheable(pmap_kernel(), vaddr);
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}
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if (cacheable)
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coherent = 0;
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/*
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* Compute the segment size, and adjust counts.
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@ -201,6 +204,8 @@ _bus_dmamap_load_buffer_direct_common(t, map, buf, buflen, p, flags,
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map->dm_segs[seg].ds_addr =
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map->dm_segs[seg]._ds_cpuaddr = curaddr;
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map->dm_segs[seg].ds_len = sgsize;
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map->dm_segs[seg]._ds_flags =
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cacheable ? 0 : BUS_DMA_COHERENT;
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first = 0;
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} else {
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if (curaddr == lastaddr &&
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@ -216,6 +221,8 @@ _bus_dmamap_load_buffer_direct_common(t, map, buf, buflen, p, flags,
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map->dm_segs[seg].ds_addr =
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map->dm_segs[seg]._ds_cpuaddr = curaddr;
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map->dm_segs[seg].ds_len = sgsize;
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map->dm_segs[seg]._ds_flags =
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cacheable ? 0 : BUS_DMA_COHERENT;
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}
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}
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@ -226,6 +233,8 @@ _bus_dmamap_load_buffer_direct_common(t, map, buf, buflen, p, flags,
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*segp = seg;
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*lastaddrp = lastaddr;
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map->_dm_flags &= ~BUS_DMA_COHERENT;
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map->_dm_flags |= coherent;
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/*
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* Did we fit?
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@ -438,6 +447,7 @@ _bus_dmamap_unload(t, map)
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*/
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map->dm_mapsize = 0;
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map->dm_nsegs = 0;
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map->_dm_flags &= ~BUS_DMA_COHERENT;
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}
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/*
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@ -467,11 +477,18 @@ _bus_dmamap_sync_0460(t, map, offset, len, ops)
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bus_size_t len;
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int ops;
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{
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bus_addr_t p, e;
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bus_addr_t p, e, ps, pe;
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bus_size_t seglen;
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int i;
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if ((ops & (BUS_DMASYNC_PREWRITE | BUS_DMASYNC_POSTREAD)) == 0)
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/* If the whole DMA map is uncached, do nothing. */
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if (map->_dm_flags & BUS_DMA_COHERENT)
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return;
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/* Short-circuit for unsupported `ops' */
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if ((ops & (BUS_DMASYNC_PREREAD |
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BUS_DMASYNC_PREWRITE |
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BUS_DMASYNC_POSTREAD)) == 0)
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return;
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for (i = 0; i < map->dm_nsegs && len > 0; i++) {
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@ -486,9 +503,16 @@ _bus_dmamap_sync_0460(t, map, offset, len, ops)
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seglen = len;
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len -= seglen;
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/* Ignore cache-inhibited segments */
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if (map->dm_segs[i]._ds_flags & BUS_DMA_COHERENT)
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continue;
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ps = map->dm_segs[i]._ds_cpuaddr + offset;
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pe = ps + seglen;
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if (ops & BUS_DMASYNC_PREWRITE) {
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p = (map->dm_segs[i]._ds_cpuaddr + offset) & ~0xf;
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e = p + ((seglen + 15) & ~0xf);
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p = ps & ~0xf;
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e = (pe + 15) & ~0xf;
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/* flush cache line (060 too) */
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while((p < e) && (p % NBPG)) {
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@ -509,9 +533,39 @@ _bus_dmamap_sync_0460(t, map, offset, len, ops)
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}
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}
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/*
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* Normally, the `PREREAD' flag instructs us to purge the
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* cache for the specified offset and length. However, if
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* the offset/length is not aligned to a cacheline boundary,
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* we may end up purging some legitimate data from the
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* start/end of the cache. In such a case, *flush* the
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* cachelines at the start and end of the required region.
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* We assume someone will do a `POSTREAD' afterwards to
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* ensure the cache is purged for the remainder of the region.
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*
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* Note: Even though the high-end MVME boards support bus-
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* snooping (well, the 060 isn't *quite* there), the osiop(4)
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* driver *ALWAYS* issues a `POSTREAD' EVEN IF NO DATA WAS
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* TRANSFERRED!
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*
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* This isn't necessarily a bug, since a SCSI target is free
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* to disconnect part way through a data-in phase anyway.
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* Thus, the CPU may never get to snoop the incoming data
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* before we purge the dmamap region.
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*
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* Note #2: All this is necessary on mvme68k because we
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* normally run the cache in Copy Back mode...
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*/
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if (ops & BUS_DMASYNC_PREREAD) {
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if (ps & 0xf)
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DCFL_40(ps);
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if (pe & 0xf)
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DCFL_40(pe);
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}
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if (ops & BUS_DMASYNC_POSTREAD) {
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p = (map->dm_segs[i]._ds_cpuaddr + offset) & ~0xf;
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e = p + ((seglen + 15) & ~0xf);
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p = ps & ~0xf;
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e = (pe + 15) & ~0xf;
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/* purge cache line */
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while((p < e) && (p % NBPG)) {
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@ -583,6 +637,7 @@ _bus_dmamem_alloc_common(t, low, high, size, alignment, boundary,
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lastaddr = VM_PAGE_TO_PHYS(m);
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segs[curseg].ds_addr = segs[curseg]._ds_cpuaddr = lastaddr;
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segs[curseg].ds_len = PAGE_SIZE;
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segs[curseg]._ds_flags = 0;
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m = m->pageq.tqe_next;
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for (; m != NULL; m = m->pageq.tqe_next) {
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@ -612,6 +667,7 @@ _bus_dmamem_alloc_common(t, low, high, size, alignment, boundary,
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segs[curseg].ds_addr =
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segs[curseg]._ds_cpuaddr = curaddr;
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segs[curseg].ds_len = PAGE_SIZE;
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segs[curseg]._ds_flags = 0;
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}
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lastaddr = curaddr;
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}
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@ -728,8 +784,11 @@ _bus_dmamem_map(t, segs, nsegs, size, kvap, flags)
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VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED);
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/* Cache-inhibit the page if necessary */
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if ( (flags & BUS_DMA_COHERENT) != 0 )
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if ((flags & BUS_DMA_COHERENT) != 0)
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_pmap_set_page_cacheinhibit(pmap_kernel(), va);
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segs[curseg]._ds_flags &= ~BUS_DMA_COHERENT;
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segs[curseg]._ds_flags |= (flags & BUS_DMA_COHERENT);
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}
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}
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pmap_update();
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.59 2001/05/13 18:35:19 scw Exp $ */
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/* $NetBSD: pmap.c,v 1.60 2001/05/16 19:06:47 scw Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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@ -2739,6 +2739,24 @@ _pmap_set_page_cacheinhibit(pm, va)
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}
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}
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int
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_pmap_page_is_cacheable(pm, va)
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struct pmap *pm;
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vaddr_t va;
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{
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pt_entry_t *pte;
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if (!pmap_ste_v(pm, va))
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return (0);
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pte = pmap_pte(pm, va);
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if (pmap_pte_ci(pte))
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return (0);
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else
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return (1);
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}
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#ifdef DEBUG
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/*
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* pmap_pvdump:
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