147 lines
5.3 KiB
C
147 lines
5.3 KiB
C
/* $NetBSD: pte.h,v 1.3 1996/07/20 20:52:43 leo Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1982, 1986, 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Utah $Hdr: pte.h 1.11 89/09/03$
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*
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* @(#)pte.h 7.3 (Berkeley) 5/8/91
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*/
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#ifndef _MACHINE_PTE_H_
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#define _MACHINE_PTE_H_
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/*
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* ATARI hardware segment/page table entries
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*/
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struct pte {
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u_int pte;
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};
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typedef u_int pt_entry_t;
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struct ste {
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u_int ste;
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};
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typedef u_int st_entry_t;
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#define PT_ENTRY_NULL ((pt_entry_t *) 0)
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#define ST_ENTRY_NULL ((st_entry_t *) 0)
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#define SG_V 0x00000002 /* segment is valid */
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#define SG_NV 0x00000000
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#define SG_PROT 0x00000004 /* access protection mask */
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#define SG_RO 0x00000004
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#define SG_RW 0x00000000
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#define SG_U 0x00000008 /* modified bit (68040) */
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#define SG_FRAME 0xffffe000
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#define SG_IMASK 0xff000000
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#define SG_ISHIFT 24
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#define SG_PMASK 0x00ffe000
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#define SG_PSHIFT 13
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/* 68040 additions */
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#define SG4_MASK1 0xfe000000 /* pointer table 1 index mask */
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#define SG4_SHIFT1 25
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#define SG4_MASK2 0x01fc0000 /* pointer table 2 index mask */
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#define SG4_SHIFT2 18
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#define SG4_MASK3 0x0003e000 /* page table index mask */
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#define SG4_SHIFT3 13
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#define SG4_ADDR1 0xfffffe00 /* pointer table address mask */
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#define SG4_ADDR2 0xffffff80 /* page table address mask */
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#define SG4_LEV1SIZE 128 /* entries in pointer table 1 */
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#define SG4_LEV2SIZE 128 /* entries in pointer table 2 */
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#define SG4_LEV3SIZE 32 /* entries in page table */
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#define PG_V 0x00000001
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#define PG_NV 0x00000000
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#define PG_PROT 0x00000004
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#define PG_U 0x00000008
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#define PG_M 0x00000010
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#define PG_W 0x00000100
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#define PG_RO 0x00000004
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#define PG_RW 0x00000000
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#define PG_FRAME 0xffffe000
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#define PG_CI 0x00000040
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#define PG_SHIFT 13
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#define PG_PFNUM(x) (((x) & PG_FRAME) >> PG_SHIFT)
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/* 68040 additions */
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#define PG_CMASK 0x00000060 /* cache mode mask */
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#define PG_CWT 0x00000000 /* writethrough caching */
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#define PG_CCB 0x00000020 /* copyback caching */
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#define PG_CIS 0x00000040 /* cache inhibited serialized */
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#define PG_CIN 0x00000060 /* cache inhibited nonserialized */
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#define PG_SO 0x00000080 /* supervisor only */
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#define ATARI_STSIZE (MAXUL2SIZE*SG4_LEV2SIZE*sizeof(st_entry_t))
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/*
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* ATARI_MAX_COREUPT maximum number of incore user page tables
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* ATARI_USER_PTSIZE the number of bytes for user pagetables
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* ATARI_PTBASE the VA start of the map from which upt's are allocated
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* ATARI_PTSIZE the size of the map from which upt's are allocated
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* ATARI_KPTSIZE size of kernel page table
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* ATARI_MAX_KPTSIZE the most number of bytes for kpt pages
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* ATARI_MAX_PTSIZE the number of bytes to map everything
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*/
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#define ATARI_MAX_COREUPT 1024
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#define ATARI_UPTSIZE roundup(VM_MAXUSER_ADDRESS / NPTEPG, NBPG)
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#define ATARI_UPTBASE 0x10000000
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#define ATARI_UPTMAXSIZE \
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roundup((ATARI_MAX_COREUPT * ATARI_UPTSIZE), NBPG)
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#define ATARI_MAX_KPTSIZE \
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(ATARI_MAX_COREUPT * ATARI_UPTSIZE / NPTEPG)
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#define ATARI_KPTSIZE \
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roundup((VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS) / NPTEPG, NBPG)
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#define ATARI_MAX_PTSIZE roundup(0xffffffff / NPTEPG, NBPG)
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/*
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* Kernel virtual address to page table entry and to physical address.
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*/
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#define kvtopte(va) \
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(&Sysmap[((unsigned)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT])
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#define ptetokv(pt) \
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((((u_int *)(pt) - Sysmap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS)
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#define kvtophys(va) \
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((kvtopte(va)->pg_pfnum << PGSHIFT) | ((int)(va) & PGOFSET))
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#endif /* !_MACHINE_PTE_H_ */
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