Checkpoint integration of 68040 MMU support. Also fix oversight in allocation
of (virtual) I/O area address range.
This commit is contained in:
leo
parent
95c6d227a5
commit
1285fe171c
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@ -1,4 +1,4 @@
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/* $NetBSD: atari_init.c,v 1.15 1996/07/12 13:14:23 leo Exp $ */
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/* $NetBSD: atari_init.c,v 1.16 1996/07/20 20:52:30 leo Exp $ */
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/*
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* Copyright (c) 1995 Leo Weppelman
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@ -64,6 +64,13 @@
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void start_c __P((int, u_int, u_int, u_int, char *));
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static void cpu_init_kcorehdr __P((u_long));
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static void mmu030_setup __P((st_entry_t *, u_int, pt_entry_t *, u_int,
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pt_entry_t *, u_int, u_int));
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#if defined(M68040) || defined(M68060)
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static void mmu040_setup __P((st_entry_t *, u_int, pt_entry_t *, u_int,
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pt_entry_t *, u_int, u_int));
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#endif
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/*
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* All info needed to generate a panic dump. All fields are setup by
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@ -76,17 +83,14 @@ static void cpu_init_kcorehdr __P((u_long));
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static cpu_kcore_hdr_t cpu_kcore_hdr;
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extern u_int lowram;
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extern u_int Sysptmap, Sysptsize, Sysseg, proc0paddr;
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extern u_int Sysptsize, Sysseg_pa, proc0paddr;
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extern pt_entry_t *Sysptmap;
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extern st_entry_t *Sysseg;
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u_int *Sysmap;
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int machineid, mmutype, cpu040, astpending;
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char *vmmap;
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pv_entry_t pv_table;
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/*
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* Need-to-know for kernel reload code.
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*/
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u_long boot_ttphystart, boot_ttphysize, boot_stphysize;
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extern char *esym;
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/*
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@ -140,13 +144,14 @@ char *esym_addr; /* Address of kernel '_esym' symbol */
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u_int pstart; /* Next available physical address*/
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u_int vstart; /* Next available virtual address */
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u_int avail;
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u_int pt, ptsize;
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pt_entry_t *pt;
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u_int ptsize;
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u_int tc, i;
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u_int *sg, *pg;
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u_int sg_proto, pg_proto;
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u_int *pg;
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u_int pg_proto;
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u_int end_loaded;
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u_int ptextra;
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u_long kbase;
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u_int kstsize;
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boot_segs[0].start = 0;
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boot_segs[0].end = stphysize;
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@ -175,7 +180,6 @@ char *esym_addr; /* Address of kernel '_esym' symbol */
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end_loaded = (u_int)end;
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else end_loaded = (u_int)esym;
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/*
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* If we have enough fast-memory to put the kernel in, do it!
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*/
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@ -200,31 +204,45 @@ char *esym_addr; /* Address of kernel '_esym' symbol */
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pstart = atari_round_page(pstart);
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avail = stphysize - pstart;
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/*
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* Calculate the number of pages needed for Sysseg.
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* For the 68030, we need 256 descriptors (segment-table-entries).
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* This easily fits into one page.
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* For the 68040, both the level-1 and level-2 descriptors are
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* stored into Sysseg. We currently handle a maximum sum of MAXKL2SIZE
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* level-1 & level-2 tables.
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*/
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#if defined(M68040) || defined(M68060)
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if (mmutype == MMU_68040)
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kstsize = MAXKL2SIZE / (NPTEPG/SG4_LEV2SIZE);
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else
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#endif
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kstsize = 1;
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/*
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* allocate the kernel segment table
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*/
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Sysseg = pstart;
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pstart += NBPG;
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avail -= NBPG;
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Sysseg = (st_entry_t *)pstart;
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pstart += kstsize * NBPG;
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avail -= kstsize * NBPG;
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/*
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* We only allocate 1 extra pagetable. it currently only contains
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* entries for Sysmap.
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* The 'pt' (the initial kernel pagetable) has to map the kernel and
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* the I/O area. To make life easy when building device drivers, the
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* I/O-area is mapped in the same VA address range as TOS maps
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* it: 0xff8000 - 0xffffff. This means that 'pt' should map at least
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* 16Mb of space. ( howmany((0xffffff/NBPG), NPTEPG)) pages).
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* Luckily, Sysptsize is twice as large and the results of mapping
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* it are checked in pmap_init() ....
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*/
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ptextra = 0;
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/*
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* allocate initial page table pages
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*/
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pt = pstart;
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ptsize = (Sysptsize + howmany(ptextra, NPTEPG)) << PGSHIFT;
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pt = (pt_entry_t *)pstart;
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ptsize = Sysptsize << PGSHIFT;
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pstart += ptsize;
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avail -= ptsize;
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/*
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* allocate kernel page table map
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*/
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Sysptmap = pstart;
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Sysptmap = (pt_entry_t *)pstart;
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pstart += NBPG;
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avail -= NBPG;
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@ -250,28 +268,14 @@ char *esym_addr; /* Address of kernel '_esym' symbol */
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Sysmap = (u_int *)(ptsize << (SEGSHIFT - PGSHIFT));
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/*
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* Initialize segment table and page table map.
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* Initialize segment tables
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*/
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sg_proto = (pt + kbase) | SG_RW | SG_V;
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pg_proto = (pt + kbase) | PG_RW | PG_CI | PG_V;
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/*
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* map so many segs
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*/
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sg = (u_int *)Sysseg;
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pg = (u_int *)Sysptmap;
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while(sg_proto < (pstart + kbase)) {
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*sg++ = sg_proto;
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*pg++ = pg_proto;
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sg_proto += NBPG;
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pg_proto += NBPG;
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}
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/*
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* invalidate the remainder of the tables
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*/
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do {
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*sg++ = SG_NV;
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*pg++ = PG_NV;
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} while(sg < (u_int *)(Sysseg + ATARI_STSIZE));
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#if defined(M68040) || defined(M68060)
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if (mmutype == MMU_68040)
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mmu040_setup(Sysseg, kstsize, pt, ptsize, Sysptmap, 1, kbase);
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else
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#endif /* defined(M68040) || defined(M68060) */
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mmu030_setup(Sysseg, kstsize, pt, ptsize, Sysptmap, 1, kbase);
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/*
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* initialize kernel page table page(s).
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@ -280,7 +284,7 @@ char *esym_addr; /* Address of kernel '_esym' symbol */
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* - Page zero is invalid
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*/
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pg_proto = (0 + kbase) | PG_RO | PG_V;
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pg = (u_int *) pt;
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pg = pt;
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*pg++ = PG_NV; pg_proto += NBPG;
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for(i = NBPG; i < (u_int)etext; i += NBPG, pg_proto += NBPG)
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*pg++ = pg_proto;
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@ -290,6 +294,28 @@ char *esym_addr; /* Address of kernel '_esym' symbol */
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*/
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pg_proto = (pg_proto & PG_FRAME) | PG_RW | PG_V;
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/*
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* Map until the segment table, the 68040/060 needs a different
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* treatment there.
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*/
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for (; i < (u_int)Sysseg; i += NBPG, pg_proto += NBPG)
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*pg++ = pg_proto;
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#if defined(M68040) || defined(M68060)
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/*
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* Map the kernel segment table cache invalidated for
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* these machines (for the 68040 not strictly necessary, but
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* recommended by Motorola; for the 68060 mandatory)
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*/
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if (mmutype == MMU_68040) {
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pg_proto |= PG_CI;
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for (; i < &Sysseg[kstsize * NPTEPG]; i += NBPG, pg_proto += NBPG)
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*pg++ = pg_proto;
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pg_proto &= ~PG_CI;
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pg_proto |= PG_CCB;
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}
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#endif /* defined(M68040) || defined(M68060) */
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/*
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* go till end of data allocated so far
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* plus proc0 u-area (to be allocated)
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@ -300,13 +326,13 @@ char *esym_addr; /* Address of kernel '_esym' symbol */
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/*
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* invalidate remainder of kernel PT
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*/
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while(pg < (u_int *)(pt + ptsize))
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while(pg < &pt[ptsize/NBPG])
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*pg++ = PG_NV;
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/*
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* Go back and validate internal IO PTEs. They MUST be Cache inhibited!
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*/
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pg = (u_int *) pt + (AD_IO / NBPG);
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pg = &pt[AD_IO / NBPG];
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pg_proto = AD_IO | PG_RW | PG_CI | PG_V;
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while(pg_proto < AD_EIO) {
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*pg++ = pg_proto;
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@ -337,7 +363,7 @@ char *esym_addr; /* Address of kernel '_esym' symbol */
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* Physcal space is already reserved!
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*/
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st_pool_virt = vstart;
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pg = (u_int *) pt + (vstart / NBPG);
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pg = &pt[vstart / NBPG];
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pg_proto = st_pool_phys | PG_RW | PG_CI | PG_V;
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vstart += st_pool_size;
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while(pg_proto < (st_pool_phys + st_pool_size)) {
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@ -352,7 +378,7 @@ char *esym_addr; /* Address of kernel '_esym' symbol */
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* copying there....).
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*/
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page_zero = vstart;
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pg = (u_int *) pt + (vstart / NBPG);
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pg = &pt[vstart / NBPG];
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*pg++ = PG_RW | PG_CI | PG_V;
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vstart += NBPG;
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*pg = PG_RW | PG_CI | PG_V | NBPG;
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@ -399,14 +425,15 @@ char *esym_addr; /* Address of kernel '_esym' symbol */
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/*
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* get the pmap module in sync with reality.
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*/
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pmap_bootstrap(vstart);
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pmap_bootstrap(vstart, AD_IO, howmany(AD_EIO-AD_IO, NBPG));
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/*
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* Prepare to enable the MMU.
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* Setup and load SRP nolimit, share global, 4 byte PTE's
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*/
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protorp[0] = 0x80000202;
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protorp[1] = Sysseg + kbase; /* + segtable address */
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protorp[1] = (u_int)Sysseg + kbase; /* + segtable address */
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Sysseg_pa = (u_int)Sysseg + kbase;
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cpu_init_kcorehdr(kbase);
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@ -545,9 +572,124 @@ u_long kbase;
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}
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cpu_kcore_hdr.mmutype = mmutype;
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cpu_kcore_hdr.kernel_pa = kbase;
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cpu_kcore_hdr.sysseg_pa = (st_entry_t *)(Sysseg + kbase);
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cpu_kcore_hdr.sysseg_pa = (st_entry_t *)((u_int)Sysseg + kbase);
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}
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void
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mmu030_setup(sysseg, kstsize, pt, ptsize, sysptmap, sysptsize, kbase)
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st_entry_t *sysseg; /* System segment table */
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u_int kstsize; /* size of 'sysseg' in pages */
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pt_entry_t *pt; /* Kernel page table */
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u_int ptsize; /* size of 'pt' in bytes */
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pt_entry_t *sysptmap; /* System page table */
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u_int sysptsize; /* size of 'sysptmap' in pages */
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u_int kbase;
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{
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st_entry_t sg_proto, *sg;
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pt_entry_t pg_proto, *pg, *epg;
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sg_proto = ((u_int)pt + kbase) | SG_RW | SG_V;
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pg_proto = ((u_int)pt + kbase) | PG_RW | PG_CI | PG_V;
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/*
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* Map the page table pages in both the HW segment table
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* and the software Sysptmap. Note that Sysptmap is also
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* considered a PT page, hence the +sysptsize.
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*/
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sg = sysseg;
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pg = sysptmap;
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epg = &pg[(ptsize >> PGSHIFT) + sysptsize];
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while(pg < epg) {
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*sg++ = sg_proto;
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*pg++ = pg_proto;
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sg_proto += NBPG;
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pg_proto += NBPG;
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}
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/*
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* invalidate the remainder of the tables
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*/
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epg = &sysptmap[sysptsize * NPTEPG];
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while(pg < epg) {
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*sg++ = SG_NV;
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*pg++ = PG_NV;
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}
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}
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#if defined(M68040) || defined(M68060)
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void
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mmu040_setup(sysseg, kstsize, pt, ptsize, sysptmap, sysptsize, kbase)
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st_entry_t *sysseg; /* System segment table */
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u_int kstsize; /* size of 'sysseg' in pages */
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pt_entry_t *pt; /* Kernel page table */
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u_int ptsize; /* size of 'pt' in bytes */
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pt_entry_t *sysptmap; /* System page table */
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u_int sysptsize; /* size of 'sysptmap' in pages */
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u_int kbase;
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{
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int i;
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st_entry_t sg_proto, *sg, *esg;
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/*
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* First invalidate the entire "segment table" pages
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* (levels 1 and 2 have the same "invalid" values).
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*/
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sg = sysseg;
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esg = &sg[kstsize * NPTEPG];
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while (sg < esg)
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*sg++ = SG_NV;
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/*
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* Initialize level 2 descriptors (which immediately
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* follow the level 1 table). These should map 'pt' + 'sysptmap'.
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* We need:
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* NPTEPG / SG4_LEV3SIZE
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* level 2 descriptors to map each of the nptpages + 1
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* pages of PTEs. Note that we set the "used" bit
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* now to save the HW the expense of doing it.
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*/
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i = ((ptsize >> PGSHIFT) + sysptsize) * (NPTEPG / SG4_LEV3SIZE);
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sg = &sysseg[SG4_LEV1SIZE];
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esg = &sg[i];
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sg_proto = ((u_int)pt + kbase) | SG_U | SG_RW | SG_V;
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while (sg < esg) {
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*sg++ = sg_proto;
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sg_proto += (SG4_LEV3SIZE * sizeof (st_entry_t));
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}
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/*
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* Initialize level 1 descriptors. We need:
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* roundup(num, SG4_LEV2SIZE) / SG4_LEVEL2SIZE
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* level 1 descriptors to map the 'num' level 2's.
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*/
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i = roundup(i, SG4_LEV2SIZE) / SG4_LEV2SIZE;
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protostfree = (-1 << (i + 1)) /* & ~(-1 << MAXKL2SIZE) */;
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sg = sysseg;
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esg = &sg[i];
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sg_proto = ((u_int)&sg[SG4_LEV1SIZE] + kbase) | SG_U | SG_RW |SG_V;
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while (sg < esg) {
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*sg++ = sg_proto;
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sg_proto += (SG4_LEV2SIZE * sizeof(st_entry_t));
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}
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/*
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* Initialize sysptmap
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*/
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sg = sysptmap;
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esg = &sg[(ptsize >> PGSHIFT) + sysptsize];
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pg_proto = ((u_int)pt + kbase) | PG_RW | PG_CI | PG_V;
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while (sg < esg) {
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*sg++ = pg_proto;
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pg_proto += NBPG;
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}
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/*
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* Invalidate rest of Sysptmap page
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*/
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esg = &sysptmap[sysptsize * NPTEPG];
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while (sg < esg)
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*sg++ = SG_NV;
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}
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#endif /* M68040 */
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#ifdef DEBUG
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void
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File diff suppressed because it is too large
Load Diff
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.h,v 1.8 1996/07/12 13:16:39 leo Exp $ */
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/* $NetBSD: pmap.h,v 1.9 1996/07/20 20:52:42 leo Exp $ */
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/*
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* Copyright (c) 1987 Carnegie-Mellon University
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@ -44,35 +44,51 @@
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#define _MACHINE_PMAP_H_
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/*
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* Pmap stuff (in anticipation of '40 support)
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* Pmap stuff
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*/
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struct pmap {
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u_int *pm_ptab; /* KVA of page table */
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u_int *pm_stab; /* KVA of segment table */
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u_int *pm_rtab; /* KVA of 68040 root table */
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int pm_stchanged; /* ST changed */
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short pm_sref; /* segment table ref count */
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short pm_count; /* pmap reference count */
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long pm_ptpages; /* more stats: PT pages */
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pt_entry_t *pm_ptab; /* KVA of page table */
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st_entry_t *pm_stab; /* KVA of segment table */
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int pm_stchanged; /* ST changed */
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int pm_stfree; /* 040: free lev2 blocks */
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u_int *pm_stpa; /* 040: ST phys. address */
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short pm_sref; /* segment table ref count */
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short pm_count; /* pmap reference count */
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long pm_ptpages; /* more stats: PT pages */
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simple_lock_data_t pm_lock; /* lock on pmap */
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struct pmap_statistics pm_stats; /* pmap statistics */
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};
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typedef struct pmap *pmap_t;
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/*
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* On the 040 we keep track of which level 2 blocks are already in use
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* with the pm_stfree mask. Bits are arranged from LSB (block 0) to MSB
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* (block 31). For convenience, the level 1 table is considered to be
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* block 0.
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*
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* MAX[KU]L2SIZE control how many pages of level 2 descriptors are allowed.
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* for the kernel and users. 16 implies only the initial "segment table"
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* page is used. WARNING: don't change MAXUL2SIZE unless you can allocate
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* physically contiguous pages for the ST in pmap.c!
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*/
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#define MAXKL2SIZE 32
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||||
#define MAXUL2SIZE 16
|
||||
#define l2tobm(n) (1 << (n))
|
||||
#define bmtol2(n) (ffs(n) - 1)
|
||||
|
||||
/*
|
||||
* Macros for speed
|
||||
*/
|
||||
#define PMAP_ACTIVATE(pmapp, pcbp, iscurproc) \
|
||||
if ((pmapp) != NULL && (pmapp)->pm_stchanged) { \
|
||||
(pcbp)->pcb_ustp = \
|
||||
atari_btop(pmap_extract(pmap_kernel(), \
|
||||
cpu040 ? (vm_offset_t)(pmapp)->pm_rtab : \
|
||||
(vm_offset_t)(pmapp)->pm_stab)); \
|
||||
atari_btop((vm_offset_t)(pmapp)->pm_stpa); \
|
||||
if (iscurproc) \
|
||||
loadustp((pcbp)->pcb_ustp); \
|
||||
(pmapp)->pm_stchanged = FALSE; \
|
||||
}
|
||||
|
||||
#define PMAP_DEACTIVATE(pmapp, pcbp)
|
||||
|
||||
/*
|
||||
|
|
@ -103,6 +119,25 @@ typedef struct pv_entry {
|
|||
#define PV_CI 0x01 /* all entries must be cache inhibited */
|
||||
#define PV_PTPAGE 0x02 /* entry maps a page table page */
|
||||
|
||||
struct pv_page;
|
||||
|
||||
struct pv_page_info {
|
||||
TAILQ_ENTRY(pv_page) pgi_list;
|
||||
struct pv_entry *pgi_freelist;
|
||||
int pgi_nfree;
|
||||
};
|
||||
|
||||
/*
|
||||
* This is basically:
|
||||
* ((NBPG - sizeof(struct pv_page_info)) / sizeof(struct pv_entry))
|
||||
*/
|
||||
#define NPVPPG 340
|
||||
|
||||
struct pv_page {
|
||||
struct pv_page_info pvp_pgi;
|
||||
struct pv_entry pvp_pv[NPVPPG];
|
||||
};
|
||||
|
||||
#ifdef _KERNEL
|
||||
/*
|
||||
* Memory segment descriptors.
|
||||
|
|
@ -130,7 +165,7 @@ struct pmap kernel_pmap_store;
|
|||
#define pmap_kernel() (&kernel_pmap_store)
|
||||
#define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count)
|
||||
|
||||
void pmap_bootstrap __P((vm_offset_t));
|
||||
void pmap_bootstrap __P((vm_offset_t, u_int, u_int));
|
||||
#endif /* _KERNEL */
|
||||
|
||||
#endif /* !_MACHINE_PMAP_H_ */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: pte.h,v 1.2 1995/04/30 14:02:14 leo Exp $ */
|
||||
/* $NetBSD: pte.h,v 1.3 1996/07/20 20:52:43 leo Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1988 University of Utah.
|
||||
|
|
@ -61,8 +61,8 @@ struct ste {
|
|||
|
||||
typedef u_int st_entry_t;
|
||||
|
||||
#define PT_ENTRY_NULL ((u_int *) 0)
|
||||
#define ST_ENTRY_NULL ((u_int *) 0)
|
||||
#define PT_ENTRY_NULL ((pt_entry_t *) 0)
|
||||
#define ST_ENTRY_NULL ((st_entry_t *) 0)
|
||||
|
||||
#define SG_V 0x00000002 /* segment is valid */
|
||||
#define SG_NV 0x00000000
|
||||
|
|
@ -84,7 +84,10 @@ typedef u_int st_entry_t;
|
|||
#define SG4_MASK3 0x0003e000 /* page table index mask */
|
||||
#define SG4_SHIFT3 13
|
||||
#define SG4_ADDR1 0xfffffe00 /* pointer table address mask */
|
||||
#define SG4_ADDR2 0xffffff00 /* page table address mask */
|
||||
#define SG4_ADDR2 0xffffff80 /* page table address mask */
|
||||
#define SG4_LEV1SIZE 128 /* entries in pointer table 1 */
|
||||
#define SG4_LEV2SIZE 128 /* entries in pointer table 2 */
|
||||
#define SG4_LEV3SIZE 32 /* entries in page table */
|
||||
|
||||
#define PG_V 0x00000001
|
||||
#define PG_NV 0x00000000
|
||||
|
|
@ -107,10 +110,8 @@ typedef u_int st_entry_t;
|
|||
#define PG_CIN 0x00000060 /* cache inhibited nonserialized */
|
||||
#define PG_SO 0x00000080 /* supervisor only */
|
||||
|
||||
#define ATARI_040RTSIZE 512 /* root (level 1) table size */
|
||||
#define ATARI_040STSIZE 512 /* segment (level 2) table size */
|
||||
#define ATARI_040PTSIZE 128 /* page (level 3) table size */
|
||||
#define ATARI_STSIZE 1024 /* segment table size */
|
||||
#define ATARI_STSIZE (MAXUL2SIZE*SG4_LEV2SIZE*sizeof(st_entry_t))
|
||||
|
||||
/*
|
||||
* ATARI_MAX_COREUPT maximum number of incore user page tables
|
||||
* ATARI_USER_PTSIZE the number of bytes for user pagetables
|
||||
|
|
|
|||
Loading…
Reference in New Issue