75caa8c729
Add support for the SMC8416 (EtherEZ) ISA ethernet card. The 8416 has an 8K shared mem (the old driver assumed 16K and failed at attach time).
419 lines
11 KiB
C
419 lines
11 KiB
C
/* $NetBSD: if_edreg.h,v 1.15 1996/01/10 16:49:22 chuck Exp $ */
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/*
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* National Semiconductor DS8390 NIC register definitions.
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*
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* Copyright (C) 1993, David Greenman. This software may be used, modified,
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* copied, distributed, and sold, in both source and binary form provided that
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* the above copyright and these terms are retained. Under no circumstances is
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* the author responsible for the proper functioning of this software, nor does
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* the author assume any responsibility for damages incurred with its use.
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*/
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/*
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* Vendor types
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*/
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#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */
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#define ED_VENDOR_3COM 0x01 /* 3Com */
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#define ED_VENDOR_NOVELL 0x02 /* Novell */
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/*
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* Compile-time config flags
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*/
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/*
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* This sets the default for enabling/disablng the tranceiver.
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*/
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#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001
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/*
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* This forces the board to be used in 8/16-bit mode even if it autoconfigs
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* differently.
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*/
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#define ED_FLAGS_FORCE_8BIT_MODE 0x0002
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#define ED_FLAGS_FORCE_16BIT_MODE 0x0004
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/*
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* This disables the use of double transmit buffers.
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*/
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#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008
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/*
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* This forces all operations with the NIC memory to use Programmed I/O (i.e.
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* not via shared memory).
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*/
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#define ED_FLAGS_FORCE_PIO 0x0010
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/*
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* Definitions for Western digital/SMC WD80x3 series ASIC
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*/
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/*
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* Memory Select Register (MSR)
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*/
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#define ED_WD_MSR 0
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/* next three definitions for Toshiba */
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#define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */
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#define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */
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#define ED_WD_MSR_LEN 0x20 /* 0 = 16-bit, 1 = 8-bit (R/W) */
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#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
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#define ED_WD_MSR_MENB 0x40 /* Memory enable */
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#define ED_WD_MSR_RST 0x80 /* Reset board */
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/*
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* Interface Configuration Register (ICR)
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*/
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#define ED_WD_ICR 1
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#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */
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#define ED_WD_ICR_OAR 0x02 /* select register (0=BIO 1=EAR) */
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#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */
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#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */
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#define ED_WD_ICR_RLA 0x10 /* recall LAN address */
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#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */
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#define ED_WD_ICR_RIO 0x40 /* recall i/o address */
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#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */
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#ifdef TOSH_ETHER
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#define ED_WD_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */
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#define ED_WD_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K,
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0x02 = 16K, 0x01 = 8K */
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/* 64K can only be used if mem address
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above 1MB */
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/* IAR holds address A23-A16 (R/W) */
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#endif
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/*
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* IO Address Register (IAR)
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*/
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#define ED_WD_IAR 2
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/*
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* EEROM Address Register
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*/
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#define ED_WD_EAR 3
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/*
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* Interrupt Request Register (IRR)
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*/
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#define ED_WD_IRR 4
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#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */
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#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */
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#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */
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#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */
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#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */
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/*
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* The three bits of the encoded IRQ are decoded as follows:
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*
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* IR2 IR1 IR0 IRQ
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* 0 0 0 2/9
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* 0 0 1 3
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* 0 1 0 5
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* 0 1 1 7
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* 1 0 0 10
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* 1 0 1 11
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* 1 1 0 15
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* 1 1 1 4
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*/
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#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */
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#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */
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#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */
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/*
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* LA Address Register (LAAR)
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*/
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#define ED_WD_LAAR 5
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#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */
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#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */
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#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */
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#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */
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/* i/o base offset to station address/card-ID PROM */
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#define ED_WD_PROM 8
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/*
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* 83C790 specific registers
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*/
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/*
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* Hardware Support Register (HWR) ('790)
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*/
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#define ED_WD790_HWR 4
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#define ED_WD790_HWR_RST 0x10 /* hardware reset */
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#define ED_WD790_HWR_LPRM 0x40 /* LAN PROM select */
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#define ED_WD790_HWR_SWH 0x80 /* switch register set */
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/*
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* ICR790 Interrupt Control Register for the 83C790
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*/
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#define ED_WD790_ICR 6
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#define ED_WD790_ICR_EIL 0x01 /* enable interrupts */
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/*
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* REV/IOPA Revision / I/O Pipe register for the 83C79X
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*/
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#define ED_WD790_REV 7
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#define ED_WD790 0x20
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#define ED_WD795 0x40
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/*
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* 79X RAM Address Register (RAR)
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* Enabled with SWH bit=1 in HWR register
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*/
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#define ED_WD790_RAR 0x0b
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#define ED_WD790_RAR_SZ8 0x00 /* 8k memory buffer */
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#define ED_WD790_RAR_SZ16 0x10 /* 16k memory buffer */
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#define ED_WD790_RAR_SZ32 0x20 /* 32k memory buffer */
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#define ED_WD790_RAR_SZ64 0x30 /* 64k memory buffer */
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/*
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* General Control Register (GCR)
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* Eanbled with SWH bit == 1 in HWR register
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*/
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#define ED_WD790_GCR 0x0d
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#define ED_WD790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */
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#define ED_WD790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */
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#define ED_WD790_GCR_ZWSEN 0x20 /* zero wait state enable */
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#define ED_WD790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */
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/*
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* The three bits of the encoded IRQ are decoded as follows:
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*
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* IR2 IR1 IR0 IRQ
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* 0 0 0 none
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* 0 0 1 9
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* 0 1 0 3
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* 0 1 1 5
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* 1 0 0 7
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* 1 0 1 10
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* 1 1 0 11
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* 1 1 1 15
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*/
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/* i/o base offset to CARD ID */
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#define ED_WD_CARD_ID ED_WD_PROM+6
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/* Board type codes in card ID */
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#define ED_TYPE_WD8003S 0x02
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#define ED_TYPE_WD8003E 0x03
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#define ED_TYPE_WD8013EBT 0x05
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#define ED_TYPE_TOSHIBA1 0x11 /* named PCETA1 */
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#define ED_TYPE_TOSHIBA2 0x12 /* named PCETA2 */
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#define ED_TYPE_TOSHIBA3 0x13 /* named PCETB */
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#define ED_TYPE_TOSHIBA4 0x14 /* named PCETC */
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#define ED_TYPE_WD8003W 0x24
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#define ED_TYPE_WD8003EB 0x25
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#define ED_TYPE_WD8013W 0x26
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#define ED_TYPE_WD8013EP 0x27
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#define ED_TYPE_WD8013WC 0x28
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#define ED_TYPE_WD8013EPC 0x29
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#define ED_TYPE_SMC8216T 0x2a
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#define ED_TYPE_SMC8216C 0x2b
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#define ED_TYPE_WD8013EBP 0x2c
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/* Bit definitions in card ID */
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#define ED_WD_REV_MASK 0x1f /* Revision mask */
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#define ED_WD_SOFTCONFIG 0x20 /* Soft config */
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#define ED_WD_LARGERAM 0x40 /* Large RAM */
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#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */
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/*
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* Checksum total. All 8 bytes in station address PROM will add up to this.
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*/
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#ifdef TOSH_ETHER
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#define ED_WD_ROM_CHECKSUM_TOTAL 0xA5
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#else
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#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF
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#endif
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#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */
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#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */
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#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */
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#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */
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/*
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* Definitions for 3Com 3c503
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*/
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#define ED_3COM_NIC_OFFSET 0
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#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */
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/*
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* XXX - The I/O address range is fragmented in the 3c503; this is the
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* number of regs at iobase.
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*/
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#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */
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/* tx memory starts in second bank on 8bit cards */
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#define ED_3COM_TX_PAGE_OFFSET_8BIT 0x20
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/* tx memory starts in first bank on 16bit cards */
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#define ED_3COM_TX_PAGE_OFFSET_16BIT 0x0
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/* ...and rx memory starts in second bank */
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#define ED_3COM_RX_PAGE_OFFSET_16BIT 0x20
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/*
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* Page Start Register. Must match PSTART in NIC.
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*/
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#define ED_3COM_PSTR 0
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/*
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* Page Stop Register. Must match PSTOP in NIC.
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*/
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#define ED_3COM_PSPR 1
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/*
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* DrQ Timer Register. Determines number of bytes to be transfered during a
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* DMA burst.
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*/
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#define ED_3COM_DQTR 2
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/*
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* Base Configuration Register. Read-only register which contains the
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* board-configured I/O base address of the adapter. Bit encoded.
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*/
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#define ED_3COM_BCFR 3
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/*
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* EPROM Configuration Register. Read-only register which contains the
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* board-configured memory base address. Bit encoded.
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*/
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#define ED_3COM_PCFR 4
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/*
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* GA Configuration Register. Gate-Array Configuration Register.
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*
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* mbs2 mbs1 mbs0 start address
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* 0 0 0 0x0000
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* 0 0 1 0x2000
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* 0 1 0 0x4000
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* 0 1 1 0x6000
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*
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* Note that with adapters with only 8K, the setting for 0x2000 must always be
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* used.
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*/
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#define ED_3COM_GACFR 5
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#define ED_3COM_GACFR_MBS0 0x01
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#define ED_3COM_GACFR_MBS1 0x02
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#define ED_3COM_GACFR_MBS2 0x04
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#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */
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#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */
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#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */
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#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */
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#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */
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/*
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* Control Register. Miscellaneous control functions.
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*/
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#define ED_3COM_CR 6
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#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */
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#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */
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#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */
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#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */
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#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */
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#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */
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#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */
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#define ED_3COM_CR_START 0x80 /* Start DMA controller */
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/*
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* Status Register. Miscellaneous status information.
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*/
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#define ED_3COM_STREG 7
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#define ED_3COM_STREG_REV 0x07 /* GA revision */
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#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */
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#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */
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#define ED_3COM_STREG_OFLW 0x20 /* Overflow */
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#define ED_3COM_STREG_UFLW 0x40 /* Underflow */
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#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */
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/*
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* Interrupt/DMA Configuration Register
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*/
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#define ED_3COM_IDCFR 8
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#define ED_3COM_IDCFR_DRQ 0x07 /* DMA request */
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#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */
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#if 0
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#define ED_3COM_IDCFR_IRQ 0xF0 /* Interrupt request */
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#else
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#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */
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#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */
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#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */
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#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */
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#endif
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/*
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* DMA Address Register MSB
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*/
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#define ED_3COM_DAMSB 9
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/*
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* DMA Address Register LSB
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*/
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#define ED_3COM_DALSB 0x0a
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/*
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* Vector Pointer Register 2
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*/
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#define ED_3COM_VPTR2 0x0b
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/*
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* Vector Pointer Register 1
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*/
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#define ED_3COM_VPTR1 0x0c
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/*
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* Vector Pointer Register 0
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*/
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#define ED_3COM_VPTR0 0x0d
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/*
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* Register File Access MSB
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*/
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#define ED_3COM_RFMSB 0x0e
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/*
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* Register File Access LSB
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*/
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#define ED_3COM_RFLSB 0x0f
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/*
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* Definitions for Novell NE1000/2000 boards
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*/
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/*
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* Board type codes
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*/
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#define ED_TYPE_NE1000 0x01
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#define ED_TYPE_NE2000 0x02
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/*
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* Register offsets/total
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*/
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#define ED_NOVELL_NIC_OFFSET 0x00
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#define ED_NOVELL_ASIC_OFFSET 0x10
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#define ED_NOVELL_IO_PORTS 32
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/*
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* Remote DMA data register; for reading or writing to the NIC mem via
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* programmed I/O (offset from ASIC base).
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*/
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#define ED_NOVELL_DATA 0x00
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/*
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* Reset register; reading from this register causes a board reset.
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*/
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#define ED_NOVELL_RESET 0x0f
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