516 lines
13 KiB
C
516 lines
13 KiB
C
/* $NetBSD: dma.c,v 1.7 1996/02/14 02:44:17 thorpej Exp $ */
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/*
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* Copyright (c) 1995 Jason R. Thorpe.
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* Copyright (c) 1982, 1990, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)dma.c 8.1 (Berkeley) 6/10/93
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*/
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/*
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* DMA driver
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/time.h>
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#include <sys/kernel.h>
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#include <sys/proc.h>
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#include <machine/cpu.h>
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#include <hp300/dev/device.h>
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#include <hp300/dev/dmareg.h>
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#include <hp300/dev/dmavar.h>
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#include <hp300/hp300/isr.h>
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extern void isrlink();
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extern void _insque();
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extern void _remque();
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extern u_int kvtop();
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extern void PCIA();
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/*
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* The largest single request will be MAXPHYS bytes which will require
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* at most MAXPHYS/NBPG+1 chain elements to describe, i.e. if none of
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* the buffer pages are physically contiguous (MAXPHYS/NBPG) and the
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* buffer is not page aligned (+1).
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*/
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#define DMAMAXIO (MAXPHYS/NBPG+1)
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struct dma_chain {
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int dc_count;
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char *dc_addr;
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};
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struct dma_channel {
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struct dma_softc *dm_softc; /* pointer back to softc */
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struct dmadevice *dm_hwaddr; /* registers if DMA_C */
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struct dmaBdevice *dm_Bhwaddr; /* registers if not DMA_C */
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char dm_flags; /* misc. flags */
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u_short dm_cmd; /* DMA controller command */
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struct dma_chain *dm_cur; /* current segment */
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struct dma_chain *dm_last; /* last segment */
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struct dma_chain dm_chain[DMAMAXIO]; /* all segments */
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};
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struct dma_softc {
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char *sc_xname; /* XXX external name */
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struct dmareg *sc_dmareg; /* pointer to our hardware */
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struct dma_channel sc_chan[NDMACHAN]; /* 2 channels */
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char sc_type; /* A, B, or C */
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} Dma_softc;
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/* types */
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#define DMA_B 0
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#define DMA_C 1
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/* flags */
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#define DMAF_PCFLUSH 0x01
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#define DMAF_VCFLUSH 0x02
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#define DMAF_NOINTR 0x04
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struct devqueue dmachan[NDMACHAN + 1];
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int dmaintr __P((void *));
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#ifdef DEBUG
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int dmadebug = 0;
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#define DDB_WORD 0x01 /* same as DMAGO_WORD */
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#define DDB_LWORD 0x02 /* same as DMAGO_LWORD */
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#define DDB_FOLLOW 0x04
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#define DDB_IO 0x08
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void dmatimeout __P((void *));
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int dmatimo[NDMACHAN];
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long dmahits[NDMACHAN];
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long dmamisses[NDMACHAN];
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long dmabyte[NDMACHAN];
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long dmaword[NDMACHAN];
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long dmalword[NDMACHAN];
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#endif
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void
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dmainit()
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{
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struct dma_softc *sc = &Dma_softc;
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struct dmareg *dma;
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struct dma_channel *dc;
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int i;
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char rev;
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/* There's just one. */
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sc->sc_dmareg = (struct dmareg *)DMA_BASE;
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dma = sc->sc_dmareg;
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sc->sc_xname = "dma0";
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/*
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* Determine the DMA type. A DMA_A or DMA_B will fail the
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* following probe.
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*
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* XXX Don't know how to easily differentiate the A and B cards,
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* so we just hope nobody has an A card (A cards will work if
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* DMAINTLVL is set to 3).
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*/
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if (badbaddr((char *)&dma->dma_id[2])) {
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rev = 'B';
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#if !defined(HP320)
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panic("dmainit: DMA card requires hp320 support");
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#endif
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} else
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rev = dma->dma_id[2];
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sc->sc_type = (rev == 'B') ? DMA_B : DMA_C;
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for (i = 0; i < NDMACHAN; i++) {
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dc = &sc->sc_chan[i];
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dc->dm_softc = sc;
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switch (i) {
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case 0:
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dc->dm_hwaddr = &dma->dma_chan0;
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dc->dm_Bhwaddr = &dma->dma_Bchan0;
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break;
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case 1:
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dc->dm_hwaddr = &dma->dma_chan1;
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dc->dm_Bhwaddr = &dma->dma_Bchan1;
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break;
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default:
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panic("dmainit: more than 2 channels?");
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/* NOTREACHED */
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}
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dmachan[i].dq_forw = dmachan[i].dq_back = &dmachan[i];
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}
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dmachan[i].dq_forw = dmachan[i].dq_back = &dmachan[i];
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#ifdef DEBUG
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/* make sure timeout is really not needed */
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timeout(dmatimeout, sc, 30 * hz);
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#endif
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printf("%s: 98620%c, 2 channels, %d bit\n", sc->sc_xname,
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rev, (rev == 'B') ? 16 : 32);
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/* Establish the interrupt handler */
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isrlink(dmaintr, sc, DMAINTLVL, ISRPRI_BIO);
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}
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int
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dmareq(dq)
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register struct devqueue *dq;
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{
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register int i;
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register int chan;
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register int s = splbio();
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chan = dq->dq_ctlr;
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i = NDMACHAN;
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while (--i >= 0) {
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if ((chan & (1 << i)) == 0)
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continue;
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if (dmachan[i].dq_forw != &dmachan[i])
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continue;
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insque(dq, &dmachan[i]);
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dq->dq_ctlr = i;
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splx(s);
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return(1);
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}
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insque(dq, dmachan[NDMACHAN].dq_back);
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splx(s);
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return(0);
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}
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void
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dmafree(dq)
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register struct devqueue *dq;
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{
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int unit = dq->dq_ctlr;
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struct dma_softc *sc = &Dma_softc;
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register struct dma_channel *dc = &sc->sc_chan[unit];
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register struct devqueue *dn;
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register int chan, s;
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s = splbio();
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#ifdef DEBUG
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dmatimo[unit] = 0;
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#endif
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DMA_CLEAR(dc);
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#if defined(HP360) || defined(HP370) || defined(HP380)
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/*
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* XXX we may not always go thru the flush code in dmastop()
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*/
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if (dc->dm_flags & DMAF_PCFLUSH) {
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PCIA();
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dc->dm_flags &= ~DMAF_PCFLUSH;
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}
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#endif
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#if defined(HP320) || defined(HP350)
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if (dc->dm_flags & DMAF_VCFLUSH) {
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/*
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* 320/350s have VACs that may also need flushing.
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* In our case we only flush the supervisor side
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* because we know that if we are DMAing to user
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* space, the physical pages will also be mapped
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* in kernel space (via vmapbuf) and hence cache-
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* inhibited by the pmap module due to the multiple
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* mapping.
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*/
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DCIS();
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dc->dm_flags &= ~DMAF_VCFLUSH;
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}
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#endif
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remque(dq);
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chan = 1 << unit;
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for (dn = dmachan[NDMACHAN].dq_forw;
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dn != &dmachan[NDMACHAN]; dn = dn->dq_forw) {
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if (dn->dq_ctlr & chan) {
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remque((caddr_t)dn);
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insque((caddr_t)dn, (caddr_t)dq->dq_back);
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splx(s);
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dn->dq_ctlr = dq->dq_ctlr;
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(dn->dq_driver->d_start)(dn->dq_unit);
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return;
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}
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}
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splx(s);
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}
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void
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dmago(unit, addr, count, flags)
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int unit;
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register char *addr;
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register int count;
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register int flags;
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{
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struct dma_softc *sc = &Dma_softc;
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register struct dma_channel *dc = &sc->sc_chan[unit];
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register struct dma_chain *dcp;
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register char *dmaend = NULL;
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register int tcount;
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if (count > MAXPHYS)
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panic("dmago: count > MAXPHYS");
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#if defined(HP320)
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if (sc->sc_type == DMA_B && (flags & DMAGO_LWORD))
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panic("dmago: no can do 32-bit DMA");
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#endif
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#ifdef DEBUG
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if (dmadebug & DDB_FOLLOW)
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printf("dmago(%d, %x, %x, %x)\n",
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unit, addr, count, flags);
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if (flags & DMAGO_LWORD)
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dmalword[unit]++;
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else if (flags & DMAGO_WORD)
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dmaword[unit]++;
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else
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dmabyte[unit]++;
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#endif
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/*
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* Build the DMA chain
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*/
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for (dcp = dc->dm_chain; count > 0; dcp++) {
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dcp->dc_addr = (char *) kvtop(addr);
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#if defined(HP380)
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/*
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* Push back dirty cache lines
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*/
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if (mmutype == MMU_68040)
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DCFP(dcp->dc_addr);
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#endif
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if (count < (tcount = NBPG - ((int)addr & PGOFSET)))
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tcount = count;
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dcp->dc_count = tcount;
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addr += tcount;
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count -= tcount;
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if (flags & DMAGO_LWORD)
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tcount >>= 2;
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else if (flags & DMAGO_WORD)
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tcount >>= 1;
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if (dcp->dc_addr == dmaend
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#if defined(HP320)
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/* only 16-bit count on 98620B */
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&& (sc->sc_type != DMA_B ||
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(dcp-1)->dc_count + tcount <= 65536)
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#endif
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) {
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#ifdef DEBUG
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dmahits[unit]++;
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#endif
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dmaend += dcp->dc_count;
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(--dcp)->dc_count += tcount;
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} else {
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#ifdef DEBUG
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dmamisses[unit]++;
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#endif
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dmaend = dcp->dc_addr + dcp->dc_count;
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dcp->dc_count = tcount;
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}
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}
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dc->dm_cur = dc->dm_chain;
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dc->dm_last = --dcp;
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dc->dm_flags = 0;
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/*
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* Set up the command word based on flags
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*/
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dc->dm_cmd = DMA_ENAB | DMA_IPL(DMAINTLVL) | DMA_START;
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if ((flags & DMAGO_READ) == 0)
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dc->dm_cmd |= DMA_WRT;
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if (flags & DMAGO_LWORD)
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dc->dm_cmd |= DMA_LWORD;
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else if (flags & DMAGO_WORD)
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dc->dm_cmd |= DMA_WORD;
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if (flags & DMAGO_PRI)
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dc->dm_cmd |= DMA_PRI;
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#if defined(HP380)
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/*
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* On the 68040 we need to flush (push) the data cache before a
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* DMA (already done above) and flush again after DMA completes.
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* In theory we should only need to flush prior to a write DMA
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* and purge after a read DMA but if the entire page is not
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* involved in the DMA we might purge some valid data.
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*/
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if (mmutype == MMU_68040 && (flags & DMAGO_READ))
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dc->dm_flags |= DMAF_PCFLUSH;
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#endif
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#if defined(HP360) || defined(HP370)
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/*
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* Remember if we need to flush external physical cache when
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* DMA is done. We only do this if we are reading (writing memory).
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*/
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if (ectype == EC_PHYS && (flags & DMAGO_READ))
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dc->dm_flags |= DMAF_PCFLUSH;
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#endif
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#if defined(HP320) || defined(HP350)
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if (ectype == EC_VIRT && (flags & DMAGO_READ))
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dc->dm_flags |= DMAF_VCFLUSH;
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#endif
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/*
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* Remember if we can skip the dma completion interrupt on
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* the last segment in the chain.
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*/
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if (flags & DMAGO_NOINT) {
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if (dc->dm_cur == dc->dm_last)
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dc->dm_cmd &= ~DMA_ENAB;
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else
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dc->dm_flags |= DMAF_NOINTR;
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}
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#ifdef DEBUG
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if (dmadebug & DDB_IO)
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if ((dmadebug&DDB_WORD) && (dc->dm_cmd&DMA_WORD) ||
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(dmadebug&DDB_LWORD) && (dc->dm_cmd&DMA_LWORD)) {
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printf("dmago: cmd %x, flags %x\n",
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dc->dm_cmd, dc->dm_flags);
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for (dcp = dc->dm_chain; dcp <= dc->dm_last; dcp++)
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printf(" %d: %d@%x\n", dcp-dc->dm_chain,
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dcp->dc_count, dcp->dc_addr);
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}
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dmatimo[unit] = 1;
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#endif
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DMA_ARM(dc);
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}
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void
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dmastop(unit)
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register int unit;
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{
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struct dma_softc *sc = &Dma_softc;
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register struct dma_channel *dc = &sc->sc_chan[unit];
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register struct devqueue *dq;
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#ifdef DEBUG
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if (dmadebug & DDB_FOLLOW)
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printf("dmastop(%d)\n", unit);
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dmatimo[unit] = 0;
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#endif
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DMA_CLEAR(dc);
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#if defined(HP360) || defined(HP370) || defined(HP380)
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if (dc->dm_flags & DMAF_PCFLUSH) {
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PCIA();
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dc->dm_flags &= ~DMAF_PCFLUSH;
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}
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#endif
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#if defined(HP320) || defined(HP350)
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if (dc->dm_flags & DMAF_VCFLUSH) {
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/*
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* 320/350s have VACs that may also need flushing.
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* In our case we only flush the supervisor side
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* because we know that if we are DMAing to user
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* space, the physical pages will also be mapped
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* in kernel space (via vmapbuf) and hence cache-
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* inhibited by the pmap module due to the multiple
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* mapping.
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*/
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DCIS();
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dc->dm_flags &= ~DMAF_VCFLUSH;
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}
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#endif
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/*
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* We may get this interrupt after a device service routine
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* has freed the dma channel. So, ignore the intr if there's
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* nothing on the queue.
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*/
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dq = dmachan[unit].dq_forw;
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if (dq != &dmachan[unit])
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(dq->dq_driver->d_done)(dq->dq_unit);
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}
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int
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dmaintr(arg)
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void *arg;
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{
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struct dma_softc *sc = arg;
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register struct dma_channel *dc;
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register int i, stat;
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int found = 0;
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#ifdef DEBUG
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if (dmadebug & DDB_FOLLOW)
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printf("dmaintr\n");
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#endif
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for (i = 0; i < NDMACHAN; i++) {
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dc = &sc->sc_chan[i];
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stat = DMA_STAT(dc);
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if ((stat & DMA_INTR) == 0)
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continue;
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found++;
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#ifdef DEBUG
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if (dmadebug & DDB_IO) {
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if ((dmadebug&DDB_WORD) && (dc->dm_cmd&DMA_WORD) ||
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(dmadebug&DDB_LWORD) && (dc->dm_cmd&DMA_LWORD))
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printf("dmaintr: unit %d stat %x next %d\n",
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i, stat, (dc->dm_cur-dc->dm_chain)+1);
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}
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if (stat & DMA_ARMED)
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printf("%s, chan %d: intr when armed\n",
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sc->sc_xname, i);
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#endif
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if (++dc->dm_cur <= dc->dm_last) {
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#ifdef DEBUG
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dmatimo[i] = 1;
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#endif
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/*
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* Last chain segment, disable DMA interrupt.
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*/
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if (dc->dm_cur == dc->dm_last &&
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(dc->dm_flags & DMAF_NOINTR))
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dc->dm_cmd &= ~DMA_ENAB;
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DMA_CLEAR(dc);
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DMA_ARM(dc);
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} else
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dmastop(i);
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}
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return(found);
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}
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#ifdef DEBUG
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void
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dmatimeout(arg)
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void *arg;
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{
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register int i, s;
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struct dma_softc *sc = arg;
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for (i = 0; i < NDMACHAN; i++) {
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s = splbio();
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if (dmatimo[i]) {
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if (dmatimo[i] > 1)
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printf("%s: timeout #%d\n", sc->sc_xname,
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|
i, dmatimo[i]-1);
|
|
dmatimo[i]++;
|
|
}
|
|
splx(s);
|
|
}
|
|
timeout(dmatimeout, sc, 30 * hz);
|
|
}
|
|
#endif
|