gavan 5232db351e The PIRSR is at location 0xffffe1ec, not 0xffffe2ec. ... Source: Intel(R) 80321 I/O Processor Developer's Manual, page 578		2003-12-16 00:04:09 +00:00
..
arm	Work-around an obscure bug (reported by a couple of people, and reproduced	2003-12-15 09:27:18 +00:00
arm32	The machdep.debug sysctl variable uses code CPU_DEBUG	2003-12-13 12:07:41 +00:00
conf	Change reference at bottom from sys/dev/majors to sys/conf/majors to match	2003-12-10 02:04:00 +00:00
footbridge	…
fpe-arm	…
include	The last cpsr_all change was misguided. Just use cpsr_c wherever possible.	2003-12-15 09:18:21 +00:00
iomd	Undo last change: The "iomd" driver has its own bus_space tag, so it didn't	2003-12-06 22:31:16 +00:00
ixp12x0	Spell address with two d's. Inspired by similar changes in OpenBSD,	2003-11-10 08:51:51 +00:00
mainbus	Fix the ARM mainbus version of bus_space_subregion() to correctly shift the	2003-12-06 22:05:33 +00:00
ofw	Enable/Restore alignment fault state on interrupt handler entry/exit.	2003-11-05 21:10:59 +00:00
s3c2xx0	…
sa11x0	Enable/Restore alignment fault state on interrupt handler entry/exit.	2003-11-05 21:10:59 +00:00
xscale	The PIRSR is at location 0xffffe1ec, not 0xffffe2ec.	2003-12-16 00:04:09 +00:00
Makefile	…