d4f824014d
- Clean up the way cpu-specific tlb/cache functions are configured
and used.
- Add a workaround for a problem whereby cpu* at superhyway? fails
to probe.
- Print more info about the cpu/cache.
- Move the RESVEC handlers back into generic sh5 code and ditch
the panic stack hack.
- Make the on-chip SCIF device the default console on Cayman.
- Add experimental support for booting via a standalone bootstrap
program (not yet committed) and using the boot parameters passed
in by it.
- Add a few more SH elf constants.
- Tick a couple of items off the TODO list.
77 lines
3.0 KiB
Plaintext
77 lines
3.0 KiB
Plaintext
$NetBSD: TODO,v 1.10 2003/03/13 13:44:16 scw Exp $
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TODO List For NetBSD/sh5
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~~~~~~~~~~~~~~~~~~~~~~~~
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In no particular order:
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DONE. Enable the cpu cache.
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There are two cache modes available in the current cpu: write-back
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and write-through. The former would be very nice. However, I don't
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want to enable caching until I'm happy enough with the stability
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of the pmap. And anyway, the pmap doesn't pay lip-service to the
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cache yet.
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DONE. Re-work the TLB invalidation code.
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This is a pain, as there is no hardware support for looking up an
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address in the TLBs. To get around this, the PTEG structure
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used to track user-space mappings contains a hint as to which group
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of four TLB slots a mapping is entered on. This information is
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maintained and updated by the TLB miss code itself. Higher level
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pmap code uses the hint to speed up TLB invalidation for user-space
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mappings (a maximum of 4 ITLB and/or 4 DTLB slots need be searched).
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Unfortunately, no such "hint" is maintained for kernel mappings
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(those in KSEG1), making KSEG1 TLB invalidations very expensive.
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Adding a "hint" field to the pmap_kernel_ipt structure would make
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things much quicker, but would use more memory... It's a question
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of trade offs.
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When I make the above change, I'd like to add a similar "hint"
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field to the PTEG structure, instead of relying on "unused" bits
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in the PTEH. This will allow the "hint" to pinpoint *exactly*
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which TLB slot in both ITLB and DTLB contains the mapping. This
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would work for both user-space and KSEG1 mappings.
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DONE. Allocate interrupt handles from a pool backed by pages from KSEG0.
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This will reduce DTLB misses at interrupt dispatch time.
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DONE. copy{in,out}() need to be re-written.
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Right now, they copy byte-at-a-time, which is not exactly fast...
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DONE. in_cksum.c needs to be replaced with an assembly code version
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which makes use of special SHmedia instructions. At first glance,
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an algorithm which makes use of the M* instructions would be
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very fast indeed.
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DONE. libkern needs sh5-specific optimised versions of key functions.
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Most of these can be used by libc too.
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7. Support for more of the on-chip peripherals, such as the DMAC.
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DONE. Test the whole lot using a 64-bit kernel/userland.
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DONE. If (8) works, try 64-bit kernel and 32-bit userland, using COMPAT32.
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10. Stress-testing of just about everything. ;-)
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DONE. Define a "board_info" structure, and move a whole bunch of currently
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hard-coded stuff into it. For example:
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- CPU speed,
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- Memory size,
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- KSEG0 physical address,
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- Cache details: e.g. size, number of sets/ways, line size,
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- Cache/TLB interface routines (currently __cpu_cache*/__cpu_tlb*)
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- etc.
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DONE. Support for nathan_sa when the branch is merged.
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DONE. In the pmap, we should clear the Referenced bit in the PTE (after
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saving its value in the mdpg_attrs/pvo, if it's a managed page)
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after purging the mapping from the cache. Right now, there are
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some cases where the cache can be purged several times for the
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same mapping, where only the first time is really necessary.
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