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A bunch of things:

Browse Source 
- Clean up the way cpu-specific tlb/cache functions are configured
    and used.
  - Add a workaround for a problem whereby cpu* at superhyway? fails
    to probe.
  - Print more info about the cpu/cache.
  - Move the RESVEC handlers back into generic sh5 code and ditch
    the panic stack hack.
  - Make the on-chip SCIF device the default console on Cayman.
  - Add experimental support for booting via a standalone bootstrap
    program (not yet committed) and using the boot parameters passed
    in by it.
  - Add a few more SH elf constants.
  - Tick a couple of items off the TODO list.
This commit is contained in:
scw 2003-03-13 13:44:16 +00:00
parent caa65123a8
commit d4f824014d
30 changed files with 942 additions and 457 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
sys/arch/evbsh5/evbsh5/cons_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cons_machdep.c,v 1.4 2002/10/19 08:43:32 scw Exp $ */
/* $NetBSD: cons_machdep.c,v 1.5 2003/03/13 13:44:20 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -112,16 +112,14 @@ consinit(void)
cninit();
#ifdef DDB
#if 0
{
extern int end;
extern int *esym;
extern void *symbol_table;
extern long symbol_table_size;
ddb_init((int)esym - (int)&end, (void *)&end, esym);
ddb_init((int)symbol_table_size, symbol_table,
(void *)((long)symbol_table + symbol_table_size));
}
#else
ddb_init(0, NULL, NULL);
#endif
if (boothowto & RB_KDB)
Debugger();
#endif
@ -149,7 +147,7 @@ comcnprobe(struct consdev *cn)
goto done;
cn->cn_dev = makedev(cdevsw_lookup_major(&com_cdevsw), 0);
pri = CN_REMOTE;
pri = CN_NORMAL;
done:
cn->cn_pri = pri;

242
sys/arch/evbsh5/evbsh5/locore.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.S,v 1.12 2003/01/20 22:25:09 scw Exp $ */
/* $NetBSD: locore.S,v 1.13 2003/03/13 13:44:20 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -43,14 +43,23 @@
/*
* The main entry point.
*
* The bootloader (to be written) will have stashed the boot parameters
* in r56 - r62
* void start(long kseg0_phys, r2
* void *symtab, r3
* vaddr_t end_kernel); r4
*
* To support the simulator, or when the kernel is loaded directly into
* memory via JTAG by the debugger, we check for end_kernel = 0 and use
* a default kseg0_phys value if necessary. C code will assume ddb
* symbols are in SYMTAB_SPACE in this case.
*
* If we were booted by the bootloader, our boot_params structure will
* be located at 'end_kernel'.
*/
.globl _C_LABEL(kernel_text)
_C_LABEL(kernel_text):
ASENTRY_NOPROFILE(text)
ASENTRY_NOPROFILE(start)
ASENTRY_NOPROFILE(text)
getcon sr, r1
LDC32(SH5_CONREG_SR_IMASK_ALL|SH5_CONREG_SR_BL|SH5_CONREG_SR_MD, r0)
or r0, r1, r0
@ -74,10 +83,26 @@ ASENTRY_NOPROFILE(start)
nop
/*
* The SR is sane. Go initialise the TLB, Cache and MMU.
* Now initialise the TLB, Cache and MMU.
*
* If we were loaded by a real bootloader, the physical address of KSEG0
* will be in r2. However, we might have been loaded over jtag, in which
* case the registers will be zero. Or, we might be running in the
* simulator, in which case the registers will be == 0xdeadbeefdeadbeef.
*/
1: LEAF(Lmapped_start, r18)
LDUC32(0x80000000, r2)
1: LDSC32(0x80000000, r0)
cmveq r4, r0, r2
LDSC64(0xdeadbeefdeadbeef, r1)
cmpeq r1, r2, r1
cmvne r1, r0, r2
cmvne r1, r63, r3
LEA(_C_LABEL(end), r0)
cmvne r1, r0, r4
LEAF(Lmapped_start, r18)
add.l r2, r63, r60 /* Save physical load address */
add.l r3, r63, r61 /* Save symbol table start */
add.l r4, r63, r62 /* Save end kernel */
pta/l Lsh5_stb1_init, tr0
blink tr0, r63
@ -85,52 +110,32 @@ ASENTRY_NOPROFILE(start)
* We are now running mapped in KSEG0, with the MMU enabled.
*/
Lmapped_start:
#ifndef SH5_SIM
LDC32(0x08000000, r56) /* RAM size. XXX: Can we probe this? */
#else
LDC32(0x01000000, r56) /* Fake 16MB for the simulator */
#endif
LEA(_C_LABEL(edata), r0)
LEA(_C_LABEL(end), r1)
cmveq r62, r1, r62 /* Fix up end_kernel, if necessary */
pta/u 1f, tr0
1: st.q r0, 0, r63 /* Clear BSS */
addi r0, 8, r0
bgtu/l r1, r0, tr0
LEA(_C_LABEL(evbsh5_bootparams), r0)
st.q r0, 0, r56 /* Save boot parameters */
st.q r0, 8, r57
st.q r0, 16, r58
st.q r0, 24, r59
st.q r0, 32, r60
st.q r0, 40, r61
st.q r0, 48, r62
/*
* Do generic runtime environment initialisation
*/
LEAF(Lsh5_init_env, r0)
ptabs/l r0, tr0
add r60, r63, r2
blink tr0, r18
/*
* Arrange to catch panic traps with the mmu off.
*/
LEA(_C_LABEL(sh5_resvec_vector_table), r0)
LEA(0x40000000, r1)
sub r0, r1, r0
ori r0, 1, r0
putcon r0, resvec
/* Now safe to call C code */
/*
* Do basic initialisation, including setting up the pmap.
*
* void evbsh5_init(vaddr_t endkernel)
* void evbsh5_init(void *symtab, vaddr_t endkernel)
*/
LEA(_C_LABEL(end), r2)
or r61, r63, r2
or r62, r63, r3
LEAF(_C_LABEL(evbsh5_init), r0)
ptabs/l r0, tr0
blink tr0, r18
@ -154,9 +159,6 @@ Lmapped_start:
blink tr0, r63
.comm Lmem_regions,SIZEOF_MEM_REGION*2,8
/*
* Pull in the common SH5 locore code
*/
@ -169,174 +171,6 @@ Lmapped_start:
#include <sh5/sh5/bus_subr.S>
/*===================== Start of RESVEC Vector Table =========================*/
_TEXT_SECTION
.balign 0x10
GLOBAL(sh5_resvec_vector_table)
/******************************************************************************
* Reset/Panic Exception Vector.
*
* RESVEC Offset: 0x0
* Length: 0x100
*/
Lsh5_resvec_vector_panic:
getcon usr, r24
putcon r15, kcr1
LEA(_C_LABEL(sh5_panic_stack) - (0x40000000-(USPACE-SZ_TRAPFRAME)), r15)
st.q r15, SFO(SF_USR,SZ_TRAPFRAME), r24 /* Save USR */
st.q r15, IFO(IF_R0,SZ_TRAPFRAME), r0 /* Save r0 */
st.q r15, IFO(IF_R1,SZ_TRAPFRAME), r1 /* Save r1 */
st.q r15, IFO(IF_R2,SZ_TRAPFRAME), r2 /* Save r2 */
getcon kcr1, r0
st.q r15, IFO(IF_R15,SZ_TRAPFRAME), r0 /* Save r15 */
gettr tr0, r0
st.q r15, IFO(IF_TR0,SZ_TRAPFRAME), r0 /* Save tr0 */
getcon pssr, r0
st.q r15, SFO(SF_SSR,SZ_TRAPFRAME), r0 /* Save PSSR */
getcon pspc, r0
st.q r15, SFO(SF_SPC,SZ_TRAPFRAME), r0 /* Save PSPC */
getcon pexpevt, r0
st.q r15, SFO(SF_EXPEVT, SZ_TRAPFRAME), r0 /* Save PEXPEVT */
getcon intevt, r0
st.q r15, SFO(SF_INTEVT, SZ_TRAPFRAME), r0 /* Save INTEVT */
getcon tea, r0
st.q r15, SFO(SF_TEA, SZ_TRAPFRAME), r0 /* Save TEA */
getcon tra, r0
st.q r15, SFO(SF_TRA, SZ_TRAPFRAME), r0 /* Save TRA */
movi 0, r2
pta/l Lsh5_event_panic, tr0
blink tr0, r63
.space (0x100 - (. - Lsh5_resvec_vector_panic))
/******************************************************************************
* Debug Synchronous Exception Handler
*
* RESVEC Offset: 0x100
* Length: 0x100
*
* We have to handle these as regular synchronous exceptions since a BRK
* instruction from userland results one of these.
*
* Trouble is, we're now running with the MMU disabled, so we do the minimum
* necessary to re-enable the MMU before jumping to the regular synchronous
* exception handler.
*/
Lsh5_resvec_vector_dbg_general:
getcon usr, r24 /* Stash USR somewhere safe for now */
putcon r0, kcr1 /* Save r0 */
getcon spc, r0 /* Fetch PC at point of exception */
putcon r0, pspc /* Make it available to real handler */
getcon ssr, r0 /* Fetch SR at point of exception */
putcon r0, pssr /* Make it available to real handler */
getcon vbr, r0
addi r0, 0x101, r0 /* The real Synchronous Exc. handler */
putcon r0, spc
getcon sr, r0 /* Arrange to set SR.MMU */
shlli r0, 32, r0
byterev r0, r0 /* This trick avoids the need to have */
ori r0, 0x80, r0 /* another register available to load */
byterev r0, r0 /* a 32-bit constant into. */
shlri r0, 32, r0
putcon r0, ssr
getcon kcr1, r0 /* Restore r0 */
putcon r24, usr /* Restore USR */
synco
rte /* Enable the MMU and jump to handler */
nop
nop
nop
nop
nop
.space (0x100 - (. - Lsh5_resvec_vector_dbg_general))
/******************************************************************************
* Debug Interrupt Handler.
*
* RESVEC Offset: 0x200
* Length: 0x200
*
* Deal with these the same way as above.
*/
Lsh5_resvec_vector_debugint:
getcon usr, r24 /* Stash USR somewhere safe for now */
putcon r0, kcr1 /* Save r0 */
getcon spc, r0 /* Fetch PC at point of exception */
putcon r0, pspc /* Make it available to real handler */
getcon ssr, r0 /* Fetch SR at point of exception */
putcon r0, pssr /* Make it available to real handler */
getcon vbr, r0
addi r0, 0x1ff, r0
addi r0, 0x1ff, r0
addi r0, 0x1ff, r0
addi r0, 0x004, r0 /* The real Asynchronous Exc. handler */
putcon r0, spc
getcon sr, r0 /* Arrange to set SR.MMU */
shlli r0, 32, r0
byterev r0, r0 /* This trick avoids the need to have */
ori r0, 0x80, r0 /* another register available to load */
byterev r0, r0 /* a 32-bit constant into. */
shlri r0, 32, r0
putcon r0, ssr
getcon kcr1, r0 /* Restore r0 */
putcon r24, usr /* Restore USR */
synco
rte /* Enable the MMU and jump to handler */
nop
nop
nop
nop
nop
/******************************************************************************
* Continuation of Panic Event.
*
* Save the remainder of the machine state, re-enable the MMU and head off
* into C code to report the problem on the console (if possible), never
* to return.
*/
Lsh5_event_panic:
_INTR_FRAME_SAVE(SZ_TRAPFRAME)
_TRAP_FRAME_SAVE(SZ_TRAPFRAME)
getcon ssr, r3 /* Parameters for panic_trap() */
getcon spc, r4
getcon expevt, r5
or r2, r63, r6
LDC32(0x01600000, r0) /* Disable (freeze) the caches */
putcfg r0, 0, r63
LDC32(0x01e00000, r0)
putcfg r0, 0, r63
LEAF(1f, r0)
putcon r0, spc
LDUC32(SH5_CONREG_SR_MD|SH5_CONREG_SR_MMU|SH5_CONREG_SR_IMASK_ALL, r0)
putcon r0, ssr
LEA(_C_LABEL(sh5_panic_stack), r15)
movi (USPACE - SZ_TRAPFRAME), r0
add r15, r0, r15
synco
rte /* Re-enable the MMU */
nop
nop
nop
nop
nop
1: LEAF(_C_LABEL(panic_trap), r0)
ptabs/l r0, tr0
or r15, r63, r2
blink tr0, r63
/*NOTREACHED*/
.comm _C_LABEL(sh5_panic_stack),USPACE,16
#include "dtfcons.h"
#if NDTFCONS > 0

159
sys/arch/evbsh5/evbsh5/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.12 2002/12/06 10:07:10 scw Exp $ */
/* $NetBSD: machdep.c,v 1.13 2003/03/13 13:44:20 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -76,7 +76,66 @@
static void compute_ctc_tick_per_us(void);
#endif
struct boot_params evbsh5_bootparams;
/*
* A reasonable default set of boot parameters, in case we were booted
* via jtag, or the simulator.
*/
struct boot_params bootparams = {
/* bp_magic */
BP_MAGIC,
/* bp_version */
BP_VERSION,
/* bp_flags */
RB_SINGLE | RB_KDB,
/* bp_kseg0_phys */
0xffffffff80000000ll,
/* bp_machine */
"Unknown machine (using \"Cayman\" defaults)",
/* bp_cpu[1] */
{
{
SH5_CPUID_STB1, /* cpuid */
0, /* version */
0x0d, /* pport */
#ifdef SH5_CPU_SPEED
SH5_CPU_SPEED*1000*1000,/* speed */
#else
256000000,
#endif
}
},
/* bp_mem[4] */
{
{
BP_MEM_TYPE_SDRAM, /* type */
0xff, /* pport */
0xfffffff80000000ll, /* physstart */
0x00800000ll /* physsize */
},
{ BP_MEM_TYPE_UNUSED },
{ BP_MEM_TYPE_UNUSED },
{ BP_MEM_TYPE_UNUSED }
},
/* bp_bootdev */
{
"/mainbus0/superhyway0,0x8/femi0,0x4000000/sysfpga0,0x1000/sm0",
"netbsd",
0
},
/* bp_consdev */
{
"/mainbus0/superhyway0,0x9/pbridge0,0x1030000/scif0",
38400
}
};
struct vm_map *exec_map;
struct vm_map *mb_map;
@ -86,8 +145,6 @@ char machine[] = MACHINE;
char cpu_model[128];
#define EVBSH5_RAM_START_PHYS 0x80000000
/*
* Physical addresses of important devices on the Cayman board
* which need to be mapped early on during bootstrap to gain
@ -105,63 +162,82 @@ char cpu_model[128];
bus_space_handle_t _evbsh5_bh_pbridge;
bus_space_handle_t _evbsh5_bh_sysfpga;
static struct mem_region mr[2];
static struct mem_region mr[BP_N_MEMBLOCKS + 1];
void *symbol_table;
long symbol_table_size;
void
evbsh5_init(vaddr_t endkernel)
evbsh5_init(void *symtab, vaddr_t endkernel)
{
extern char sh5_panic_stack[];
#if NDTFCONS > 0
extern char *_dtf_buffer;
extern void _dtf_trap_frob(void);
vaddr_t dtfbuf;
paddr_t frob_p;
#endif
struct boot_params *bp;
u_long ksize;
vsize_t size;
caddr_t v;
paddr_t kseg0_phys;
int i, j;
bp = (struct boot_params *)endkernel;
if (bp->bp_magic == BP_MAGIC && bp->bp_version == BP_VERSION)
bootparams = *bp;
else
symtab = (void *)endkernel; /* Assume no symbol table */
bp = &bootparams;
kseg0_phys = (paddr_t)bp->bp_kseg0_phys;
symbol_table = symtab;
symbol_table_size = (long)endkernel - (long)symtab;
cpu_identify();
endkernel = sh5_round_page(endkernel);
ksize = sh5_round_page(endkernel - SH5_KSEG0_BASE);
ksize = endkernel - SH5_KSEG0_BASE;
for (i = j = 0; i < BP_N_MEMBLOCKS; i++) {
paddr_t pa;
psize_t ps;
mr[0].mr_start = EVBSH5_RAM_START_PHYS + ksize;
mr[0].mr_kvastart = SH5_KSEG0_BASE + ksize;
mr[0].mr_size = sh5_trunc_page(evbsh5_bootparams.bp_physramsize)- ksize;
mr[1].mr_start = 0;
mr[1].mr_size = 0;
if (bp->bp_mem[i].type != BP_MEM_TYPE_SDRAM)
continue;
pmap_bootstrap(endkernel, EVBSH5_RAM_START_PHYS, mr);
pa = (paddr_t) bp->bp_mem[i].physstart;
ps = (psize_t) bp->bp_mem[i].physsize;
__asm __volatile("putcon %0, sr" :: "r"(SH5_CONREG_SR_IMASK_ALL));
if (pa == kseg0_phys) {
pa += ksize;
ps -= ksize;
}
/* XXX: Will need to be revisited for SMP */
curcpu()->ci_panicstkphys = EVBSH5_RAM_START_PHYS +
(((uintptr_t)&sh5_panic_stack[0]) - SH5_KSEG0_BASE) +
(USPACE - sizeof(struct trapframe));
mr[j].mr_start = pa;
mr[j].mr_size = ps;
/*
* Fix up the cpu-specific TLB/cache manipulation functions
*/
__cpu_tlbinv_cookie = _sh5_stb1_tlbinv_cookie;
__cpu_tlbinv_all = _sh5_stb1_tlbinv_all;
__cpu_tlbload = _sh5_stb1_tlbload;
__cpu_cache_dpurge = _sh5_stb1_cache_dpurge;
__cpu_cache_dpurge_iinv = _sh5_stb1_cache_dpurge_iinv;
__cpu_cache_dinv = _sh5_stb1_cache_dinv;
__cpu_cache_dinv_iinv = _sh5_stb1_cache_dinv_iinv;
__cpu_cache_iinv = _sh5_stb1_cache_iinv;
__cpu_cache_iinv_all = _sh5_stb1_cache_iinv_all;
__cpu_cache_purge_all = _sh5_stb1_cache_purge_all;
if (pa >= kseg0_phys &&
(pa + ps) < (kseg0_phys + SH5_KSEG0_SIZE))
mr[j].mr_kvastart = SH5_KSEG0_BASE + (pa - kseg0_phys);
else
mr[j].mr_kvastart = SH5_KSEG1_SIZE;
j++;
}
mr[j].mr_start = 0;
mr[j].mr_size = 0;
pmap_bootstrap(endkernel, kseg0_phys, mr);
#if NDTFCONS > 0
dtfbuf = (vaddr_t) &_dtf_buffer;
frob_p = (paddr_t) (uintptr_t) _dtf_trap_frob;
frob_p = EVBSH5_RAM_START_PHYS + (frob_p - SH5_KSEG0_BASE);
frob_p = kseg0_phys + (frob_p - SH5_KSEG0_BASE);
dtf_init(0xc100018, frob_p,
(paddr_t)(EVBSH5_RAM_START_PHYS + (dtfbuf - SH5_KSEG0_BASE)),
dtfbuf);
(paddr_t)(kseg0_phys + (dtfbuf - SH5_KSEG0_BASE)), dtfbuf);
#endif
/*
@ -182,7 +258,7 @@ evbsh5_init(vaddr_t endkernel)
_sh5_ctc_ticks_per_us = SH5_CPU_SPEED;
#endif
boothowto = RB_SINGLE | RB_KDB;
boothowto = bp->bp_flags;
/*
* Call allocsys() now so we can steal pages from KSEG0.
@ -316,10 +392,10 @@ cpu_startup(void)
nmbclusters * mclbytes, VM_MAP_INTRSAFE,
FALSE, NULL);
strcpy(cpu_model, "SuperH SH5");
strcpy(cpu_model, bootparams.bp_machine);
printf("%s%s, %d-bit mode\n", version, cpu_model,
(sizeof(void *) == 8) ? 64 : 32);
printf("%s%s running in %d-bit mode at %dMHz\n", version, cpu_model,
(sizeof(void *) == 8) ? 64 : 32, (u_int)_sh5_ctc_ticks_per_us);
format_bytes(pbuf, sizeof(pbuf), ctob(physmem));
printf("total memory = %s\n", pbuf);
format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free));
@ -359,11 +435,6 @@ cpu_reboot(int how, char *bootstr)
;
}
void
device_register(struct device *dev, void *arg)
{
}
void
sh5_nmi_clear(void)
{

4
sys/arch/evbsh5/evbsh5/machdep.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.h,v 1.2 2002/10/22 09:30:27 scw Exp $ */
/* $NetBSD: machdep.h,v 1.3 2003/03/13 13:44:20 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -41,6 +41,6 @@
extern bus_space_handle_t _evbsh5_bh_pbridge;
extern bus_space_handle_t _evbsh5_bh_sysfpga;
extern void evbsh5_init(vaddr_t);
extern void evbsh5_init(void *, vaddr_t);
#endif /* _EVBSH5_MACHDEP_H */

4
sys/arch/evbsh5/include/Makefile
View File

@ -1,9 +1,9 @@
# $NetBSD: Makefile,v 1.10 2003/01/19 19:49:58 scw Exp $
# $NetBSD: Makefile,v 1.11 2003/03/13 13:44:21 scw Exp $
INCSDIR= /usr/include/evbsh5
INCS= alphaledio.h ansi.h aout_machdep.h asm.h \
bswap.h \
bootparams.h bswap.h \
cdefs.h conreg.h cpu.h \
db_machdep.h disklabel.h \
elf_machdep.h endian.h endian_machdep.h \

47
sys/arch/evbsh5/include/bootparams.h
View File

@ -1,46 +1,3 @@
/* $NetBSD: bootparams.h,v 1.1 2002/07/05 13:31:42 scw Exp $ */
/* $NetBSD: bootparams.h,v 1.2 2003/03/13 13:44:21 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Steve C. Woodford for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _EVBSH5_BOOTPARAMS_H
#define _EVBSH5_BOOTPARAMS_H
struct boot_params {
u_int64_t bp_physramsize;
u_int64_t bp_resvd[6];
};
#endif /* _EVBSH5_BOOTPARAMS_H */
#include <sh5/bootparams.h>

66
sys/arch/evbsh5/include/loadfile_machdep.h Normal file
View File

@ -0,0 +1,66 @@
/* $NetBSD: loadfile_machdep.h,v 1.1 2003/03/13 13:44:21 scw Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Steve C. Woodford for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __EVBSH5_LOADFILE_MACHDEP_H
#define __EVBSH5_LOADFILE_MACHDEP_H
#define BOOT_ELF32
#define LOAD_KERNEL LOAD_ALL
#define COUNT_KERNEL COUNT_ALL
#define LOADADDR(a) (((u_long)(a)) + offset)
#define ALIGNENTRY(a) ((u_long)(a))
#define READ(f, b, c) read((f), (void *)LOADADDR(b), (c))
#define BCOPY(s, d, c) memcpy((void *)LOADADDR(d), (void *)(s), (c))
#define BZERO(d, c) memset((void *)LOADADDR(d), 0, (c))
#ifdef _STANDALONE
#define WARN(a) (void)(printf a, \
printf((errno ? ": %s\n" : "\n"), \
strerror(errno)))
#define PROGRESS(a) (void) printf a
#define ALLOC(a) alloc(a)
#define FREE(a, b) free(a, b)
#else
#define WARN(a) warn a
#define PROGRESS(a) /* nothing */
#define ALLOC(a) malloc(a)
#define FREE(a, b) free(a)
#endif
#endif /* __EVBSH5_LOADFILE_MACHDEP_H */

6
sys/arch/sh5/TODO
View File

@ -1,4 +1,4 @@
$NetBSD: TODO,v 1.9 2002/11/23 09:27:03 scw Exp $
$NetBSD: TODO,v 1.10 2003/03/13 13:44:16 scw Exp $
TODO List For NetBSD/sh5
~~~~~~~~~~~~~~~~~~~~~~~~
@ -57,7 +57,7 @@ DONE. If (8) works, try 64-bit kernel and 32-bit userland, using COMPAT32.
10. Stress-testing of just about everything. ;-)
11. Define a "board_info" structure, and move a whole bunch of currently
DONE. Define a "board_info" structure, and move a whole bunch of currently
hard-coded stuff into it. For example:
- CPU speed,
@ -67,7 +67,7 @@ DONE. If (8) works, try 64-bit kernel and 32-bit userland, using COMPAT32.
- Cache/TLB interface routines (currently __cpu_cache*/__cpu_tlb*)
- etc.
12. Support for nathan_sa when the branch is merged.
DONE. Support for nathan_sa when the branch is merged.
DONE. In the pmap, we should clear the Referenced bit in the PTE (after
saving its value in the mdpg_attrs/pvo, if it's a managed page)

3
sys/arch/sh5/conf/files.sh5
View File

@ -1,4 +1,4 @@
# $NetBSD: files.sh5,v 1.10 2002/10/19 09:01:44 scw Exp $
# $NetBSD: files.sh5,v 1.11 2003/03/13 13:44:17 scw Exp $
#
@ -121,6 +121,7 @@ file arch/sh5/sh5/autoconf.c
file arch/sh5/sh5/bus_dma.c
file arch/sh5/sh5/bus_space.c
file arch/sh5/sh5/conf.c
file arch/sh5/sh5/cpu_ident.c
file arch/sh5/sh5/db_disasm.c ddb
file arch/sh5/sh5/db_interface.c ddb
file arch/sh5/sh5/db_memrw.c ddb

90
sys/arch/sh5/dev/cpu_sh.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu_sh.c,v 1.4 2002/10/02 15:52:36 thorpej Exp $ */
/* $NetBSD: cpu_sh.c,v 1.5 2003/03/13 13:44:17 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -44,10 +44,13 @@
#include <sys/systm.h>
#include <sys/device.h>
#include <machine/bootparams.h>
#include <machine/cacheops.h>
#include <machine/cpu.h>
#include <machine/bus.h>
#include <machine/intr.h>
#include <sh5/sh5/stb1var.h>
#include <sh5/dev/superhywayvar.h>
#include "locators.h"
@ -59,28 +62,18 @@ CFATTACH_DECL(cpu_sh, sizeof(struct device),
cpu_shmatch, cpu_shattach, NULL, NULL);
extern struct cfdriver cpu_cd;
#define CPU_SH_MODULE_ID 0x51e2
static void cpu_prcache(struct device *, struct sh5_cache_info *, const char *);
/*ARGSUSED*/
static int
cpu_shmatch(struct device *parent, struct cfdata *cf, void *args)
{
struct superhyway_attach_args *sa = args;
bus_space_handle_t bh;
u_int64_t vcr;
if (strcmp(sa->sa_name, cpu_cd.cd_name))
return (0);
sa->sa_pport = 0;
bus_space_map(sa->sa_bust,
SUPERHYWAY_PPORT_TO_BUSADDR(cf->cf_loc[SUPERHYWAYCF_PPORT]),
SUPERHYWAY_REG_SZ, 0, &bh);
vcr = bus_space_read_8(sa->sa_bust, bh, SUPERHYWAY_REG_VCR);
bus_space_unmap(sa->sa_bust, bh, SUPERHYWAY_REG_SZ);
if (SUPERHYWAY_VCR_MOD_ID(vcr) != CPU_SH_MODULE_ID)
if (cf->cf_loc[SUPERHYWAYCF_PPORT] != bootparams.bp_cpu[0].pport)
return (0);
sa->sa_pport = cf->cf_loc[SUPERHYWAYCF_PPORT];
@ -95,12 +88,79 @@ cpu_shattach(struct device *parent, struct device *self, void *args)
struct superhyway_attach_args *sa = args;
bus_space_handle_t bh;
u_int64_t vcr;
u_int cpuid, version;
const char *cpustr;
char str[64];
bus_space_map(sa->sa_bust, SUPERHYWAY_PPORT_TO_BUSADDR(sa->sa_pport),
SUPERHYWAY_REG_SZ, 0, &bh);
vcr = bus_space_read_8(sa->sa_bust, bh, SUPERHYWAY_REG_VCR);
bus_space_unmap(sa->sa_bust, bh, SUPERHYWAY_REG_SZ);
printf(": SH-5 CPU, Version 0x%x\n",
(int) SUPERHYWAY_VCR_MOD_VERS(vcr));
/*
* There seems to be a hardware bug which causes reads of CPU.VCR
* to return zero under certain circumstances.
*/
if (vcr == 0) {
cpuid = bootparams.bp_cpu[0].cpuid;
version = bootparams.bp_cpu[0].version;
} else {
cpuid = SUPERHYWAY_VCR_MOD_ID(vcr);
version = SUPERHYWAY_VCR_MOD_VERS(vcr);
}
switch (cpuid) {
case SH5_CPUID_STB1:
cpustr = "SH5 STB1 Evaluation Silicon";
break;
default:
sprintf(str, "Unknown CPU ID: 0x%x", cpuid);
cpustr = str;
break;
}
printf("\n%s: %s, Version %d, %d.%02d MHz\n", self->dv_xname, cpustr,
version, bootparams.bp_cpu[0].speed / 1000000,
(bootparams.bp_cpu[0].speed % 1000000) / 10000);
if (sh5_cache_ops.iinfo.type == SH5_CACHE_INFO_TYPE_NONE) {
/* Unified cache. */
cpu_prcache(self, &sh5_cache_ops.dinfo, "Unified");
} else {
/* Separate I/D caches */
cpu_prcache(self, &sh5_cache_ops.dinfo, "D");
cpu_prcache(self, &sh5_cache_ops.iinfo, "I");
}
}
static void
cpu_prcache(struct device *dv, struct sh5_cache_info *ci, const char *name)
{
static const char *ctype[] = {NULL, "VIVT", "VIPT", "PIPT"};
static const char *wtype[] = {NULL, "thru", "back"};
int i;
i = (strcmp(name, "I") == 0);
if (ci->type == 0 || ci->type >= (sizeof(ctype)/sizeof(char *))) {
printf("%s: WARNING: Invalid %s-cache type: %d\n",
dv->dv_xname, name, ci->type);
ci->type = SH5_CACHE_INFO_TYPE_VIVT; /* XXX: Safe default */
}
if (i == 0 &&
(ci->write == 0 || ci->write >= (sizeof(wtype)/sizeof(char *)))) {
printf("%s: WARNING: Invalid %s-cache write type: %d\n",
dv->dv_xname, name, ci->write);
ci->write = SH5_CACHE_INFO_WRITE_BACK; /* XXX: Safe default */
}
printf("%s: %s-cache %d KB %db/line %d-way %d-sets %s", dv->dv_xname,
name, ci->size / 1024, ci->line_size, ci->nways,
ci->nsets, ctype[ci->type]);
if (i == 0)
printf(" write-%s", wtype[ci->write]);
printf("\n");
}

4
sys/arch/sh5/include/Makefile
View File

@ -1,9 +1,9 @@
# $NetBSD: Makefile,v 1.11 2003/01/19 19:49:47 scw Exp $
# $NetBSD: Makefile,v 1.12 2003/03/13 13:44:17 scw Exp $
INCSDIR= /usr/include/sh5
INCS= ansi.h aout_machdep.h asm.h \
bswap.h byte_swap.h \
bootparams.h bswap.h byte_swap.h \
cdefs.h conreg.h cpu.h cputypes.h \
disklabel.h \
elf_machdep.h endian.h endian_machdep.h \

103
sys/arch/sh5/include/bootparams.h Normal file
View File

@ -0,0 +1,103 @@
/* $NetBSD: bootparams.h,v 1.1 2003/03/13 13:44:17 scw Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Steve C. Woodford for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _SH5_BOOTPARAMS_H
#define _SH5_BOOTPARAMS_H
#define BP_N_MEMBLOCKS 4 /* Handle 4 chunks of RAM */
#define BP_N_CPUS 1 /* Handle 1 cpu (no SMP yet) */
#define BP_PATH_STRING_LEN 128 /* Length of path/dev strings */
/*
* This is the structure passed in from the boot loader.
*/
struct boot_params {
/* Magic number */
u_int bp_magic;
#define BP_MAGIC 0xcafebabe /* bp_magic number */
/* Structure version number */
u_int bp_version;
#define BP_VERSION 0x00000001 /* structure version number */
/* Boot Flags (RB_SINGLE, RB_KDB, etc) */
u_int bp_flags;
/* Physical address of start of KSEG0 */
int64_t bp_kseg0_phys;
/* Machine identifier string */
char bp_machine[64];
/* CPU parameters */
struct {
u_int cpuid;
#define BP_CPUID_UNUSED 0xffffffff
u_int version;
u_int pport;
u_int64_t speed;
} bp_cpu[BP_N_CPUS];
/* Memory parameters */
struct {
u_int type;
#define BP_MEM_TYPE_UNUSED 0
#define BP_MEM_TYPE_SDRAM 1
u_int pport;
int64_t physstart;
int64_t physsize;
} bp_mem[BP_N_MEMBLOCKS];
/* Locator for the device we booted from */
struct {
char dev[BP_PATH_STRING_LEN];
char path[BP_PATH_STRING_LEN];
u_int partition;
} bp_bootdev;
/* Locator for the console device */
struct {
char dev[BP_PATH_STRING_LEN];
u_int speed;
} bp_consdev;
};
#if defined(_KERNEL) || defined(_STANDALONE)
extern struct boot_params bootparams;
#endif
#endif /* _SH5_BOOTPARAMS_H */

52
sys/arch/sh5/include/cacheops.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cacheops.h,v 1.5 2002/10/07 14:48:14 scw Exp $ */
/* $NetBSD: cacheops.h,v 1.6 2003/03/13 13:44:17 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -45,12 +45,48 @@
*/
#define SH5_CACHELINE_SIZE 32
extern void (*__cpu_cache_dpurge)(vaddr_t, paddr_t, vsize_t);
extern void (*__cpu_cache_dpurge_iinv)(vaddr_t, paddr_t, vsize_t);
extern void (*__cpu_cache_dinv)(vaddr_t, paddr_t, vsize_t);
extern void (*__cpu_cache_dinv_iinv)(vaddr_t, paddr_t, vsize_t);
extern void (*__cpu_cache_iinv)(vaddr_t, paddr_t, vsize_t);
extern void (*__cpu_cache_iinv_all)(void);
extern void (*__cpu_cache_purge_all)(void);
struct sh5_cache_info {
u_int size;
u_char type;
u_char write;
u_short line_size;
u_short nways;
u_short nsets;
};
#define SH5_CACHE_INFO_TYPE_NONE 0
#define SH5_CACHE_INFO_TYPE_VIVT 1
#define SH5_CACHE_INFO_TYPE_VIPT 2
#define SH5_CACHE_INFO_TYPE_PI 3
#define SH5_CACHE_INFO_WRITE_NONE 0
#define SH5_CACHE_INFO_WRITE_THRU 1
#define SH5_CACHE_INFO_WRITE_BACK 2
struct sh5_cache_ops {
void (*dpurge)(vaddr_t, paddr_t, vsize_t);
void (*dpurge_iinv)(vaddr_t, paddr_t, vsize_t);
void (*dinv)(vaddr_t, paddr_t, vsize_t);
void (*dinv_iinv)(vaddr_t, paddr_t, vsize_t);
void (*iinv)(vaddr_t, paddr_t, vsize_t);
void (*iinv_all)(void);
void (*purge_all)(void);
struct sh5_cache_info dinfo;
struct sh5_cache_info iinfo;
};
#define cpu_cache_dpurge sh5_cache_ops.dpurge
#define cpu_cache_dpurge_iinv sh5_cache_ops.dpurge_iinv
#define cpu_cache_dinv sh5_cache_ops.dinv
#define cpu_cache_dinv_iinv sh5_cache_ops.dinv_iinv
#define cpu_cache_iinv sh5_cache_ops.iinv
#define cpu_cache_iinv_all sh5_cache_ops.iinv_all
#define cpu_cache_purge_all sh5_cache_ops.purge_all
#define cpu_cache_dinfo sh5_cache_ops.dinfo
#define cpu_cache_iinfo sh5_cache_ops.iinfo
#ifdef _KERNEL
extern struct sh5_cache_ops sh5_cache_ops;
#endif
#endif /* __SH5_CACHEOPS_H */

4
sys/arch/sh5/include/cpu.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.9 2003/01/19 19:49:48 scw Exp $ */
/* $NetBSD: cpu.h,v 1.10 2003/03/13 13:44:18 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -143,7 +143,6 @@ struct cpu_info {
vsid_t ci_curvsid; /* current pmap's vsid */
u_int ci_want_resched; /* current process pre-empted */
volatile u_int ci_intr_depth; /* nesting level of interrupts */
paddr_t ci_panicstkphys; /* panic stack top physical address */
struct exc_scratch_frame ci_escratch; /* exception scratch area */
struct tlb_scratch_frame ci_tscratch; /* TLB miss scratch area */
};
@ -253,6 +252,7 @@ struct pcb;
extern void savectx(struct pcb *);
extern void dumpsys(void);
extern void cpu_identify(void);
extern void sh5_reboot(int, char *);
#endif /* _KERNEL */

10
sys/arch/sh5/include/elf_machdep.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: elf_machdep.h,v 1.2 2002/07/11 21:20:23 scw Exp $ */
/* $NetBSD: elf_machdep.h,v 1.3 2003/03/13 13:44:18 scw Exp $ */
#ifndef _BYTE_ORDER
#error Define _BYTE_ORDER!
@ -76,6 +76,14 @@
#define R_SH_DIR10SW 49
#define R_SH_DIR10SL 50
#define R_SH_DIR10SQ 51
#define R_SH_TLS_GD_32 144
#define R_SH_TLS_LD_32 145
#define R_SH_TLS_LDO_32 146
#define R_SH_TLS_IE_32 147
#define R_SH_TLS_LE_32 148
#define R_SH_TLS_DTPMOD32 149
#define R_SH_TLS_DTPOFF32 150
#define R_SH_TLS_TPOFF32 151
#define R_SH_GOT32 160
#define R_SH_PLT32 161
#define R_SH_COPY 162

20
sys/arch/sh5/include/pmap.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap.h,v 1.14 2003/01/19 19:49:50 scw Exp $ */
/* $NetBSD: pmap.h,v 1.15 2003/03/13 13:44:18 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -106,9 +106,21 @@ extern u_int pmap_ipt_hash(vsid_t vsid, vaddr_t va); /* See exception.S */
extern vaddr_t pmap_map_device(paddr_t, u_int);
extern int pmap_page_is_cacheable(pmap_t, vaddr_t);
extern void (*__cpu_tlbinv_cookie)(pteh_t, tlbcookie_t);
extern void (*__cpu_tlbinv_all)(void);
extern void (*__cpu_tlbload)(void); /* Not C-callable */
struct sh5_tlb_ops {
void (*tlbinv_cookie)(pteh_t, tlbcookie_t);
void (*tlbinv_all)(void);
void (*tlbload)(void); /* Not C-callable */
u_int dtlb_slots;
u_int itlb_slots;
};
#define cpu_tlbinv_cookie sh5_tlb_ops.tlbinv_cookie
#define cpu_tlbinv_all sh5_tlb_ops.tlbinv_all
#define cpu_tlbload sh5_tlb_ops.tlbload
#define cpu_dtlb_slots sh5_tlb_ops.dtlb_slots
#define cpu_itlb_slots sh5_tlb_ops.itlb_slots
extern struct sh5_tlb_ops sh5_tlb_ops;
#endif
#endif /* _SH5_PMAP_H */

4
sys/arch/sh5/include/trap.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: trap.h,v 1.8 2003/01/19 19:49:51 scw Exp $ */
/* $NetBSD: trap.h,v 1.9 2003/03/13 13:44:18 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -115,7 +115,7 @@ extern void userret(struct lwp *);
extern void trap(struct lwp *, struct trapframe *);
extern void trapa(struct lwp *, struct trapframe *);
extern void panic_trap(struct trapframe *, register_t, register_t,
register_t, int);
register_t);
extern const char *trap_type(int);
#if defined(DIAGNOSTIC) || defined(DDB)
extern void dump_trapframe(void (*)(const char *, ...), const char *,

7
sys/arch/sh5/sh5/autoconf.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: autoconf.c,v 1.2 2002/08/26 10:24:57 scw Exp $ */
/* $NetBSD: autoconf.c,v 1.3 2003/03/13 13:44:18 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -73,3 +73,8 @@ cpu_rootconf(void)
setroot(booted_device, bootpart);
}
void
device_register(struct device *dev, void *aux)
{
}

10
sys/arch/sh5/sh5/bus_dma.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: bus_dma.c,v 1.6 2002/10/08 15:56:13 scw Exp $ */
/* $NetBSD: bus_dma.c,v 1.7 2003/03/13 13:44:18 scw Exp $ */
/*-
* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
@ -39,7 +39,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.6 2002/10/08 15:56:13 scw Exp $");
__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.7 2003/03/13 13:44:18 scw Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -541,7 +541,7 @@ _bus_dmamap_sync_helper(vaddr_t va, paddr_t pa, vsize_t len, int inv)
if (len == 0)
return;
op = inv ? __cpu_cache_dinv : __cpu_cache_dpurge;
op = inv ? cpu_cache_dinv : cpu_cache_dpurge;
/*
* Align the region to a cache-line boundary by always purging
@ -550,7 +550,7 @@ _bus_dmamap_sync_helper(vaddr_t va, paddr_t pa, vsize_t len, int inv)
if ((va & (SH5_CACHELINE_SIZE - 1)) != 0) {
bytes = (vsize_t)va & (SH5_CACHELINE_SIZE - 1);
bytes = min(SH5_CACHELINE_SIZE - bytes, len);
__cpu_cache_dpurge(va & ~(SH5_CACHELINE_SIZE - 1),
cpu_cache_dpurge(va & ~(SH5_CACHELINE_SIZE - 1),
pa & ~(SH5_CACHELINE_SIZE - 1), SH5_CACHELINE_SIZE);
if ((len -= bytes) == 0)
return;
@ -564,7 +564,7 @@ _bus_dmamap_sync_helper(vaddr_t va, paddr_t pa, vsize_t len, int inv)
*/
if ((len & (SH5_CACHELINE_SIZE - 1)) != 0) {
bytes = min((vsize_t)len & (SH5_CACHELINE_SIZE - 1), len);
__cpu_cache_dpurge(va + (len - bytes), pa + (len - bytes),
cpu_cache_dpurge(va + (len - bytes), pa + (len - bytes),
SH5_CACHELINE_SIZE);
if ((len -= bytes) == 0)
return;

121
sys/arch/sh5/sh5/cpu_ident.c Normal file
View File

@ -0,0 +1,121 @@
/* $NetBSD: cpu_ident.c,v 1.1 2003/03/13 13:44:18 scw Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Steve C. Woodford for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/types.h>
#include <uvm/uvm_extern.h>
#include <machine/cacheops.h>
#include <machine/cpu.h>
#include <machine/pmap.h>
#include <machine/bootparams.h>
#include <sh5/sh5/stb1var.h>
struct sh5_cache_ops sh5_cache_ops;
struct sh5_tlb_ops sh5_tlb_ops;
/*
* The STB1 was the first "Evaluation" implementation of the SH5
* architecture. We use its cache/tlb description in the case where
* we don't recognise the CPU ID.
*
* This is enough to limp along to the point where we can bitch to
* the user that their cpu is not supported.
*/
static struct sh5_cache_ops stb1_cache_ops = {
_sh5_stb1_cache_dpurge,
_sh5_stb1_cache_dpurge_iinv,
_sh5_stb1_cache_dinv,
_sh5_stb1_cache_dinv_iinv,
_sh5_stb1_cache_iinv,
_sh5_stb1_cache_iinv_all,
_sh5_stb1_cache_purge_all,
{
/* Data cache */
STB1_CACHE_SIZE,
SH5_CACHE_INFO_TYPE_VIPT,
SH5_CACHE_INFO_WRITE_BACK,
STB1_CACHE_LINE_SIZE,
STB1_CACHE_NWAYS,
STB1_CACHE_NSETS
},
{
/* Instruction cache */
STB1_CACHE_SIZE,
SH5_CACHE_INFO_TYPE_VIVT,
SH5_CACHE_INFO_WRITE_NONE,
STB1_CACHE_LINE_SIZE,
STB1_CACHE_NWAYS,
STB1_CACHE_NSETS
}
};
static struct sh5_tlb_ops stb1_tlb_ops = {
_sh5_stb1_tlbinv_cookie,
_sh5_stb1_tlbinv_all,
_sh5_stb1_tlbload,
STB1_TLB_NSLOTS,
STB1_TLB_NSLOTS
};
void
cpu_identify(void)
{
struct boot_params *bp = &bootparams;
switch (bp->bp_cpu[0].cpuid) {
#ifdef CPU_STB1
case SH5_CPUID_STB1:
sh5_cache_ops = stb1_cache_ops;
sh5_tlb_ops = stb1_tlb_ops;
break;
#endif
default:
/*
* Default to the STB1 ops.
* We'll bitch later about lack of specific cpu support.
*/
sh5_cache_ops = stb1_cache_ops;
sh5_tlb_ops = stb1_tlb_ops;
break;
}
}

20
sys/arch/sh5/sh5/dtf_comms.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: dtf_comms.c,v 1.2 2002/09/12 12:38:42 scw Exp $ */
/* $NetBSD: dtf_comms.c,v 1.3 2003/03/13 13:44:18 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -229,13 +229,13 @@ dtf_get_args(void)
trap_v->dt_magic = DTF_ASEBRK_GETARGS;
trap_v->dt_params = (u_int32_t)params_p;
__cpu_cache_dpurge((vaddr_t)trap_v, trap_p, sizeof(struct dtf_trap));
cpu_cache_dpurge((vaddr_t)trap_v, trap_p, sizeof(struct dtf_trap));
params_v->dp_desc = (u_int32_t)packet_p;
__cpu_cache_dpurge((vaddr_t)params_v, params_p,
cpu_cache_dpurge((vaddr_t)params_v, params_p,
sizeof(struct dtf_params));
__cpu_cache_dinv((vaddr_t)packet_v, packet_p, DTF_MAX_PACKET_LEN);
cpu_cache_dinv((vaddr_t)packet_v, packet_p, DTF_MAX_PACKET_LEN);
_dtf_trap(dtf_fpfreg_p, trap_p, dtf_frob_p);
@ -261,16 +261,16 @@ static int
dtf_send_packet(void)
{
__cpu_cache_dpurge((vaddr_t)packet_v, packet_p, DTF_MAX_PACKET_LEN);
cpu_cache_dpurge((vaddr_t)packet_v, packet_p, DTF_MAX_PACKET_LEN);
trap_v->dt_magic = DTF_ASEBRK_DTF;
trap_v->dt_params = (u_int32_t)params_p;
__cpu_cache_dpurge((vaddr_t)trap_v, trap_p, sizeof(struct dtf_trap));
cpu_cache_dpurge((vaddr_t)trap_v, trap_p, sizeof(struct dtf_trap));
params_v->dp_desc = (u_int32_t)packet_p;
params_v->dp_cid = 0;
params_v->dp_direction = DTF_DIRECTION_TARGET2HOST;
__cpu_cache_dpurge((vaddr_t)params_v, params_p,
cpu_cache_dpurge((vaddr_t)params_v, params_p,
sizeof(struct dtf_params));
_dtf_trap(dtf_fpfreg_p, trap_p, dtf_frob_p);
@ -284,15 +284,15 @@ dtf_recv_packet(u_int16_t cid)
trap_v->dt_magic = DTF_ASEBRK_DTF;
trap_v->dt_params = (u_int32_t)params_p;
__cpu_cache_dpurge((vaddr_t)trap_v, trap_p, sizeof(struct dtf_trap));
cpu_cache_dpurge((vaddr_t)trap_v, trap_p, sizeof(struct dtf_trap));
params_v->dp_desc = (u_int32_t)packet_p;
params_v->dp_cid = cid;
params_v->dp_direction = DTF_DIRECTION_HOST2TARGET;
__cpu_cache_dpurge((vaddr_t)params_v, params_p,
cpu_cache_dpurge((vaddr_t)params_v, params_p,
sizeof(struct dtf_params));
__cpu_cache_dinv((vaddr_t)packet_v, packet_p, DTF_MAX_PACKET_LEN);
cpu_cache_dinv((vaddr_t)packet_v, packet_p, DTF_MAX_PACKET_LEN);
_dtf_trap(dtf_fpfreg_p, trap_p, dtf_frob_p);

235
sys/arch/sh5/sh5/exception.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: exception.S,v 1.20 2003/01/19 19:49:53 scw Exp $ */
/* $NetBSD: exception.S,v 1.21 2003/03/13 13:44:18 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -481,16 +481,66 @@
.balign 0x100
GLOBAL(sh5_vector_table)
.space (0x100 - (. - _C_LABEL(sh5_vector_table)))
/******************************************************************************
* Panic Exception Handler (bounced here by RESVEC panic handler)
*
* VBR Offset: 0x0
* Length: 0x100
*
* This vector is always entered via the first-stage handler in the
* RESVEC vector table. At this point, the MMU is enabled, r0 and r1
* contain the saved values for PSPC and PSSR respectively, r24 contains
* the EXPEVT which caused tha panic. (The real PEXPEVT just before the
* panic is in EXPEVT as a result of the 'rte' instruction in the first-
* stage handler.)
*
* The values originally in r0/r1 are saved in kcr1/dcr respectively.
*
* Note that USR was unavoidably tainted by stores to r0, r1, and r24 in
* the first-stage handler.
*/
Lsh5_vector_panic:
putcon r0, pspc /* Recover PSPC */
putcon r1, pssr /* and PSSR */
getcon usr, r1 /* Don't taint USR any further */
putcon r15, kcr1
LEA(_C_LABEL(sh5_panic_stack), r15)
movi (USPACE - SZ_TRAPFRAME), r0
add r15, r0, r15
st.q r15, SFO(SF_USR,SZ_TRAPFRAME), r1 /* Save USR */
getcon kcr1, r0
st.q r15, IFO(IF_R0,SZ_TRAPFRAME), r0 /* Save r0 */
getcon dcr, r0
st.q r15, IFO(IF_R1,SZ_TRAPFRAME), r0 /* Save r1 */
st.q r15, IFO(IF_R2,SZ_TRAPFRAME), r2 /* Save r2 */
getcon kcr1, r0
st.q r15, IFO(IF_R15,SZ_TRAPFRAME), r0 /* Save r15 */
gettr tr0, r0
st.q r15, IFO(IF_TR0,SZ_TRAPFRAME), r0 /* Save tr0 */
getcon pssr, r0
st.q r15, SFO(SF_SSR,SZ_TRAPFRAME), r0 /* Save PSSR */
getcon pspc, r0
st.q r15, SFO(SF_SPC,SZ_TRAPFRAME), r0 /* Save PSPC */
getcon expevt, r0
st.q r15, SFO(SF_EXPEVT, SZ_TRAPFRAME), r0 /* Save (P)EXPEVT */
getcon intevt, r0
st.q r15, SFO(SF_INTEVT, SZ_TRAPFRAME), r0 /* Save INTEVT */
getcon tea, r0
st.q r15, SFO(SF_TEA, SZ_TRAPFRAME), r0 /* Save TEA */
getcon tra, r0
st.q r15, SFO(SF_TRA, SZ_TRAPFRAME), r0 /* Save TRA */
pta/l Lsh5_event_panic, tr0
blink tr0, r63
.space (0x100 - (. - Lsh5_vector_panic))
/******************************************************************************
* Non-TLB Miss Synchronous Exception Handler
*
* VBR Offset: 0x100
* Length: 0x100
*
* XXX: This handler very nearly fills the 0x100 byte exception slot :XXX
* Length: 0x300
*/
Lsh5_vector_general:
_EXCEPTION_ENTRY(SZ_TRAPFRAME, CRIT_SYNC_EXCEPTION)
@ -627,8 +677,8 @@ Lsh5_vector_tlbmiss:
* of returning.
*/
Ltlbmiss_updatetlb:
LEA(_C_LABEL(__cpu_tlbload), r2)
LDPTR r2, 0, r2
LEA(_C_LABEL(sh5_tlb_ops), r2)
LDPTR r2, CPU_TLBLOAD, r2
ptabs/l r2, tr0
blink tr0, r2
@ -1243,6 +1293,177 @@ Lsh5_critical_fault:
#endif /* PORTMASTER */
/*===================== Start of RESVEC Vector Table =========================*/
_TEXT_SECTION
.balign 0x10
GLOBAL(sh5_resvec_vector_table)
/******************************************************************************
* Reset/Panic Exception Vector.
*
* RESVEC Offset: 0x0
* Length: 0x100
*
* Come here when a gross error occurs. This is generally when the cpu wants
* to take a synchronous exception, but they're blocked by SR.BL being set.
*
* By now, the MMU is off, and the program counter/status register values
* at the instant of the panic are saved in PSPC/PSSR. Since we'd like to
* use these registers to arrange for the MMU to be re-enabled, we have to
* free up two GPRs to save them. Unfortunately, we cannot then spare a GPR
* to save USR. Fortunately, there's no point in going out of our way to
* preserve USR since we're about to die anyway and USR provides little useful
* state in this case.
*
* Note: We should consider ensuring KCR0 is sane ...
*/
Lsh5_resvec_vector_panic:
putcon r0, kcr1
putcon r1, dcr
getcon pspc, r0 /* Preserve PSPC in r0 */
getcon pssr, r1 /* Preserve PSSR in r1 */
getcon spc, r24 /* Fetch PC at point of exception */
putcon r24, pspc /* Make it available to real handler */
getcon ssr, r24 /* Fetch SR at point of exception */
putcon r24, pssr /* Make it available to real handler */
getcon vbr, r24
addi r24, 0x1, r24 /* The real Panic Exception handler */
putcon r24, spc
getcon sr, r24 /* Arrange to set SR.MMU */
shlli r24, 32, r24
byterev r24, r24 /* This trick avoids the need to have */
ori r24, 0x80, r24 /* another register available to load */
byterev r24, r24 /* a 32-bit constant into. */
shlri r24, 32, r24
putcon r24, ssr
getcon expevt, r24 /* Preserve panic event code */
synco
rte /* Enable the MMU and jump to handler */
nop
nop
nop
nop
nop
.space (0x100 - (. - Lsh5_resvec_vector_panic))
/******************************************************************************
* Debug Synchronous Exception Handler
*
* RESVEC Offset: 0x100
* Length: 0x100
*
* We have to handle these as regular synchronous exceptions since a BRK
* instruction from userland results one of these.
*
* Trouble is, we're now running with the MMU disabled, so we do the minimum
* necessary to re-enable the MMU before jumping to the regular synchronous
* exception handler.
*/
Lsh5_resvec_vector_dbg_general:
getcon usr, r24 /* Stash USR somewhere safe for now */
putcon r0, dcr /* Save r0 */
getcon spc, r0 /* Fetch PC at point of exception */
putcon r0, pspc /* Make it available to real handler */
getcon ssr, r0 /* Fetch SR at point of exception */
putcon r0, pssr /* Make it available to real handler */
getcon expevt, r0 /* Fetch EXPEVT at point of exception */
putcon r0, pexpevt /* Make it available to real handler */
getcon vbr, r0
addi r0, 0x101, r0 /* The real Synchronous Exc. handler */
putcon r0, spc
getcon sr, r0 /* Arrange to set SR.MMU */
shlli r0, 32, r0
byterev r0, r0 /* This trick avoids the need to have */
ori r0, 0x80, r0 /* another register available to load */
byterev r0, r0 /* a 32-bit constant into. */
shlri r0, 32, r0
putcon r0, ssr
getcon dcr, r0 /* Restore r0 */
putcon r24, usr /* Restore USR */
synco
rte /* Enable the MMU and jump to handler */
nop
nop
nop
nop
nop
.space (0x100 - (. - Lsh5_resvec_vector_dbg_general))
/******************************************************************************
* Debug Interrupt Handler.
*
* RESVEC Offset: 0x200
* Length: 0x200
*
* Deal with these the same way as above.
*/
Lsh5_resvec_vector_debugint:
getcon usr, r24 /* Stash USR somewhere safe for now */
putcon r0, dcr /* Save r0 */
getcon spc, r0 /* Fetch PC at point of exception */
putcon r0, pspc /* Make it available to real handler */
getcon ssr, r0 /* Fetch SR at point of exception */
putcon r0, pssr /* Make it available to real handler */
getcon expevt, r0 /* Fetch EXPEVT at point of exception */
putcon r0, pexpevt /* Make it available to real handler */
getcon vbr, r0
addi r0, 0x1ff, r0
addi r0, 0x1ff, r0
addi r0, 0x1ff, r0
addi r0, 0x004, r0 /* The real Asynchronous Exc. handler */
putcon r0, spc
getcon sr, r0 /* Arrange to set SR.MMU */
shlli r0, 32, r0
byterev r0, r0 /* This trick avoids the need to have */
ori r0, 0x80, r0 /* another register available to load */
byterev r0, r0 /* a 32-bit constant into. */
shlri r0, 32, r0
putcon r0, ssr
getcon dcr, r0 /* Restore r0 */
putcon r24, usr /* Restore USR */
synco
rte /* Enable the MMU and jump to handler */
nop
nop
nop
nop
nop
/******************************************************************************
* Continuation of Panic Event.
*
* Save the remainder of the machine state and head off into C code to
* report the problem on the console (if possible), never to return.
*/
Lsh5_event_panic:
_INTR_FRAME_SAVE(SZ_TRAPFRAME)
_TRAP_FRAME_SAVE(SZ_TRAPFRAME)
getcon ssr, r3 /* Parameters for panic_trap() */
getcon spc, r4
or r24, r63, r5
getcon sr, r1 /* Fetch current status register */
ori r1, SH5_CONREG_SR_IMASK_ALL, r0
putcon r0, sr /* Block async exceptions */
LDC32(SH5_CONREG_SR_BL, r2) /* Unblock exceptions. This allows */
andc r0, r2, r0 /* us to take a TLB miss exception */
andc r1, r2, r1
putcon r0, sr /* Now safe to cause TLB miss */
LEAF(_C_LABEL(panic_trap), r0)
ptabs/l r0, tr0
or r15, r63, r2
blink tr0, r63
/*NOTREACHED*/
.comm _C_LABEL(sh5_panic_stack),USPACE,16
/******************************************************************************
*
* void Lcheck_softint(void) [Note: Do not call directly from C code]

16
sys/arch/sh5/sh5/genassym.cf
View File

@ -1,4 +1,4 @@
# $NetBSD: genassym.cf,v 1.14 2003/01/19 19:49:54 scw Exp $
# $NetBSD: genassym.cf,v 1.15 2003/03/13 13:44:19 scw Exp $
# Copyright 2002 Wasabi Systems, Inc.
# All rights reserved.
@ -50,6 +50,7 @@ include <netinet/ip_var.h>
include <uvm/uvm_extern.h>
include <machine/cpu.h>
include <machine/cacheops.h>
include <machine/frame.h>
include <machine/pcb.h>
include <machine/trap.h>
@ -79,7 +80,6 @@ define CI_CURPCB offsetof(struct cpu_info, ci_curpcb)
define CI_CURVSID offsetof(struct cpu_info, ci_curvsid)
define CI_WANT_RESCHED offsetof(struct cpu_info, ci_want_resched)
define CI_INTR_DEPTH offsetof(struct cpu_info, ci_intr_depth)
define CI_PANICSTKPHYS offsetof(struct cpu_info, ci_panicstkphys)
define CI_ESCRATCH offsetof(struct cpu_info, ci_escratch)
define CI_TSCRATCH offsetof(struct cpu_info, ci_tscratch)
@ -381,3 +381,15 @@ define IP_SRC offsetof(struct ip, ip_src)
define IP_DST offsetof(struct ip, ip_dst)
define IP6_SRC offsetof(struct ip6_hdr, ip6_src)
define IP6_DST offsetof(struct ip6_hdr, ip6_dst)
# Cache/TLB constants
define CPU_CACHE_DPURGE offsetof(struct sh5_cache_ops, dpurge)
define CPU_CACHE_DPURGE_IINV offsetof(struct sh5_cache_ops, dpurge_iinv)
define CPU_CACHE_DINV offsetof(struct sh5_cache_ops, dinv)
define CPU_CACHE_DINV_IINV offsetof(struct sh5_cache_ops, dinv_iinv)
define CPU_CACHE_IINV offsetof(struct sh5_cache_ops, iinv)
define CPU_CACHE_IINV_ALL offsetof(struct sh5_cache_ops, iinv_all)
define CPU_CACHE_PURGE_ALL offsetof(struct sh5_cache_ops, purge_all)
define CPU_TLBINV_COOKIE offsetof(struct sh5_tlb_ops, tlbinv_cookie)
define CPU_TLBINV_ALL offsetof(struct sh5_tlb_ops, tlbinv_all)
define CPU_TLBLOAD offsetof(struct sh5_tlb_ops, tlbload)

14
sys/arch/sh5/sh5/locore_subr.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore_subr.S,v 1.16 2003/01/19 19:49:54 scw Exp $ */
/* $NetBSD: locore_subr.S,v 1.17 2003/03/13 13:44:19 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -58,6 +58,8 @@
*
* To be called early on from port-specific locore.S, after the MMU is
* enabled, but before pmap_bootstrap().
*
* On entry, r2 must point to the physical address of KSEG0.
*/
Lsh5_init_env:
/*
@ -68,6 +70,16 @@ Lsh5_init_env:
LEA(_C_LABEL(sh5_vector_table), r0)
putcon r0, vbr
/*
* Arrange to catch debug/panic exceptions with the mmu off.
* Need to convert sh5_resvec_vector_table to a physical
* address.
*/
LEA(_C_LABEL(sh5_resvec_vector_table) - SH5_KSEG0_BASE, r0)
add r0, r2, r0 /* Convert to phys address */
ori r0, 1, r0 /* MMU off when handling exceptions */
putcon r0, resvec
/*
* If we have an FPU, ensure it's quiescent
*/

54
sys/arch/sh5/sh5/pmap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap.c,v 1.27 2003/01/19 19:49:55 scw Exp $ */
/* $NetBSD: pmap.c,v 1.28 2003/03/13 13:44:19 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -263,15 +263,6 @@ u_int pmap_pteg_bits; /* Number of bits set in pmap_pteg_mask */
*/
kpte_t pmap_kernel_ipt[KERNEL_IPT_SIZE];
/*
* These are initialised, at boot time by cpu-specific code, to point
* to cpu-specific functions.
*/
void (*__cpu_tlbinv_cookie)(pteh_t, tlbcookie_t);
void (*__cpu_tlbinv_all)(void);
void (*__cpu_tlbload)(void); /* Not callable from C */
/*
* This structure serves a double purpose as over-flow table entry
* and for tracking phys->virt mappings.
@ -663,7 +654,7 @@ pmap_cache_sync_raise(vaddr_t va, ptel_t ptel, ptel_t clrbits)
* The page is being made no-exec, rd-only.
* Purge the data cache and invalidate insn cache.
*/
__cpu_cache_dpurge_iinv(va, pa, NBPG);
cpu_cache_dpurge_iinv(va, pa, NBPG);
break;
case SH5_PTEL_PR_W:
@ -671,7 +662,7 @@ pmap_cache_sync_raise(vaddr_t va, ptel_t ptel, ptel_t clrbits)
* The page is being made read-only.
* Purge the data-cache.
*/
__cpu_cache_dpurge(va, pa, NBPG);
cpu_cache_dpurge(va, pa, NBPG);
break;
case SH5_PTEL_PR_X:
@ -679,7 +670,7 @@ pmap_cache_sync_raise(vaddr_t va, ptel_t ptel, ptel_t clrbits)
* The page is being made no-exec.
* Invalidate the instruction cache.
*/
__cpu_cache_iinv(va, pa, NBPG);
cpu_cache_iinv(va, pa, NBPG);
break;
case 0:
@ -721,7 +712,7 @@ pmap_cache_sync_unmap(vaddr_t va, ptel_t ptel)
* The page was executable, and possibly writable.
* Purge the data cache and invalidate insn cache.
*/
__cpu_cache_dpurge_iinv(va, pa, NBPG);
cpu_cache_dpurge_iinv(va, pa, NBPG);
break;
case SH5_PTEL_PR_W:
@ -729,7 +720,7 @@ pmap_cache_sync_unmap(vaddr_t va, ptel_t ptel)
* The page was writable.
* Purge the data-cache.
*/
__cpu_cache_dpurge(va, pa, NBPG);
cpu_cache_dpurge(va, pa, NBPG);
break;
case 0:
@ -737,13 +728,13 @@ pmap_cache_sync_unmap(vaddr_t va, ptel_t ptel)
* The page was read-only.
* Just invalidate the data cache.
*
* Note: We'd like to use __cpu_cache_dinv() here, but
* Note: We'd like to use cpu_cache_dinv() here, but
* since the mapping may still be in the TLB, the cache
* tag will contain the original protection bits.
* The invalidate operation will actually cause a write-
* protection fault (!!!!) in this case.
*/
__cpu_cache_dpurge(va, pa, NBPG);
cpu_cache_dpurge(va, pa, NBPG);
break;
}
}
@ -788,7 +779,7 @@ pmap_pteg_clear_bit(volatile pte_t *pt, struct pvo_entry *pvo, u_int ptebit)
* The mapping may be cached in the TLB. Call cpu-specific
* code to check and invalidate if necessary.
*/
__cpu_tlbinv_cookie((pteh & SH5_PTEH_EPN_MASK) |
cpu_tlbinv_cookie((pteh & SH5_PTEH_EPN_MASK) |
(pm->pm_asid << SH5_PTEH_ASID_SHIFT),
pt->tlbcookie);
}
@ -807,7 +798,7 @@ pmap_kpte_clear_bit(int idx, struct pvo_entry *pvo, ptel_t ptebit)
ptel = pmap_kernel_ipt_get_ptel(kpte);
if ((ptel & SH5_PTEL_R) != 0)
__cpu_tlbinv_cookie((pteh_t)PVO_VADDR(pvo) | SH5_PTEH_SH,
cpu_tlbinv_cookie((pteh_t)PVO_VADDR(pvo) | SH5_PTEH_SH,
pmap_kernel_ipt_get_tlbcookie(kpte));
pmap_kernel_ipt_set_tlbcookie(kpte, 0);
@ -881,7 +872,7 @@ pmap_pteg_unset(volatile pte_t *pt, struct pvo_entry *pvo)
* The mapping may be in the TLB. Call cpu-specific
* code to check and invalidate if necessary.
*/
__cpu_tlbinv_cookie((pteh & SH5_PTEH_EPN_MASK) |
cpu_tlbinv_cookie((pteh & SH5_PTEH_EPN_MASK) |
(pm->pm_asid << SH5_PTEH_ASID_SHIFT),
pt->tlbcookie);
}
@ -1129,6 +1120,11 @@ pmap_bootstrap(vaddr_t avail, paddr_t kseg0base, struct mem_region *mr)
avail_start = mr[0].mr_start;
/*
* It should now be safe to take TLB miss exceptions.
*/
__asm __volatile("putcon %0, sr" :: "r"(SH5_CONREG_SR_IMASK_ALL));
/*
* Tell UVM about physical memory
*/
@ -1531,7 +1527,7 @@ pmap_copyzero_page_dpurge(paddr_t pa, struct evcnt *ev)
if (PVO_VADDR(pvo) < SH5_KSEG0_BASE && !PVO_PTEGIDX_ISSET(pvo))
continue;
__cpu_cache_dpurge_iinv(PVO_VADDR(pvo), pa, NBPG);
cpu_cache_dpurge_iinv(PVO_VADDR(pvo), pa, NBPG);
ev->ev_count++;
@ -1658,7 +1654,7 @@ pmap_pa_unmap_kva(vaddr_t kva, kpte_t *kpte)
pmap_cache_sync_unmap(kva, oldptel);
if ((oldptel & SH5_PTEL_R) != 0) {
__cpu_tlbinv_cookie(
cpu_tlbinv_cookie(
((pteh_t)kva & SH5_PTEH_EPN_MASK) | SH5_PTEH_SH,
pmap_kernel_ipt_get_tlbcookie(kpte));
}
@ -2597,8 +2593,8 @@ pmap_activate(struct lwp *l)
* on a context switch, do it now. But only if we're
* not resuming in the same pmap context.
*/
if (__cpu_cache_iinv_all && old_vsid != pm->pm_vsid)
__cpu_cache_iinv_all();
if (cpu_cache_iinv_all && old_vsid != pm->pm_vsid)
cpu_cache_iinv_all();
}
}
@ -2788,9 +2784,9 @@ pmap_asid_alloc(pmap_t pm)
* We do need to invalidate the TLB, however.
*/
#if 0
__cpu_cache_purge_all();
cpu_cache_purge_all();
#endif
__cpu_tlbinv_all();
cpu_tlbinv_all();
pmap_asid_generation++;
pmap_asid_next = PMAP_ASID_USER_START;
@ -2870,11 +2866,11 @@ pmap_write_trap(struct proc *p, int usermode, vaddr_t va)
* other TLB miss in the meantime).
*/
if (SH5_PTEL_CACHEABLE(pvo->pvo_ptel)) {
__cpu_cache_dpurge(PVO_VADDR(pvo),
cpu_cache_dpurge(PVO_VADDR(pvo),
(paddr_t)(pvo->pvo_ptel & SH5_PTEL_PPN_MASK), NBPG);
}
__cpu_tlbinv_cookie((pteh_t)PVO_VADDR(pvo) | SH5_PTEH_SH,
cpu_tlbinv_cookie((pteh_t)PVO_VADDR(pvo) | SH5_PTEH_SH,
pmap_kernel_ipt_get_tlbcookie(kpte));
pmap_kernel_ipt_set_tlbcookie(kpte, 0);
@ -2926,7 +2922,7 @@ pmap_unmap_poolpage(vaddr_t va)
if (mp->mr_size && mp->mr_kvastart < SH5_KSEG1_BASE) {
pa = mp->mr_start + (paddr_t)(va - mp->mr_kvastart);
__cpu_cache_dpurge(va, pa, NBPG);
cpu_cache_dpurge(va, pa, NBPG);
return (pa);
}

6
sys/arch/sh5/sh5/process_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: process_machdep.c,v 1.11 2003/01/20 20:07:54 scw Exp $ */
/* $NetBSD: process_machdep.c,v 1.12 2003/03/13 13:44:19 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -124,8 +124,8 @@ setregs(struct lwp *l, struct exec_package *pack, u_long stack)
* Until such time as the cause is determined and fixed, this works
* around the problem.
*/
if (__cpu_cache_iinv_all)
__cpu_cache_iinv_all();
if (cpu_cache_iinv_all)
cpu_cache_iinv_all();
}
int

10
sys/arch/sh5/sh5/sh5_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: sh5_machdep.c,v 1.5 2002/10/07 14:48:14 scw Exp $ */
/* $NetBSD: sh5_machdep.c,v 1.6 2003/03/13 13:44:19 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -68,14 +68,6 @@ u_int _sh5_ctc_ticks_per_us;
*/
u_int _sh5_delay_constant;
void (*__cpu_cache_dpurge)(vaddr_t, paddr_t, vsize_t);
void (*__cpu_cache_dpurge_iinv)(vaddr_t, paddr_t, vsize_t);
void (*__cpu_cache_dinv)(vaddr_t, paddr_t, vsize_t);
void (*__cpu_cache_dinv_iinv)(vaddr_t, paddr_t, vsize_t);
void (*__cpu_cache_iinv)(vaddr_t, paddr_t, vsize_t);
void (*__cpu_cache_iinv_all)(void);
void (*__cpu_cache_purge_all)(void);
/*
* These variables are needed by /sbin/savecore
*/

8
sys/arch/sh5/sh5/stb1_locore.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: stb1_locore.S,v 1.9 2002/11/23 09:25:55 scw Exp $ */
/* $NetBSD: stb1_locore.S,v 1.10 2003/03/13 13:44:20 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -44,10 +44,11 @@
* ##########
*/
#include <sh5/sh5/stb1var.h>
/*
* Manifest constants describing the TLB layout
*/
#define STB1_TLB_NSLOTS 64
#define STB1_TLB_IDX_STEP 16
#define STB1_TLB_IDX_SHIFT 4
#define STB1_DTLB(idx) (0x00800000 + (STB1_TLB_IDX_STEP * (idx)))
@ -57,9 +58,6 @@
/*
* Ditto for the cache
*/
#define STB1_CACHE_NWAYS 4
#define STB1_CACHE_NSETS 256
#define STB1_CACHE_LINE_SIZE 32
#define STB1_ICCR (0x01600000)
#define STB1_OCCR (0x01e00000)
#define STB1_OCACHETAG0(w,s) (0x01800000 + ((w) * 65536) + ((s) * 16))

13
sys/arch/sh5/sh5/stb1var.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: stb1var.h,v 1.4 2002/11/23 09:25:55 scw Exp $ */
/* $NetBSD: stb1var.h,v 1.5 2003/03/13 13:44:20 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -38,6 +38,7 @@
#ifndef _STB1VAR_H
#define _STB1VAR_H
#ifndef _LOCORE
#include <sh5/pte.h>
extern void _sh5_stb1_tlbinv_cookie(pteh_t, tlbcookie_t);
@ -50,5 +51,15 @@ extern void _sh5_stb1_cache_dinv_iinv(vaddr_t, paddr_t, vsize_t);
extern void _sh5_stb1_cache_iinv(vaddr_t, paddr_t, vsize_t);
extern void _sh5_stb1_cache_iinv_all(void);
extern void _sh5_stb1_cache_purge_all(void);
#endif /* _LOCORE */
#define SH5_CPUID_STB1 0x51e2
#define STB1_TLB_NSLOTS 64
#define STB1_CACHE_SIZE 0x8000
#define STB1_CACHE_LINE_SIZE 32
#define STB1_CACHE_NWAYS 4
#define STB1_CACHE_NSETS 256
#endif /* _STB1VAR_H */

51
sys/arch/sh5/sh5/trap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: trap.c,v 1.18 2003/01/20 22:32:26 scw Exp $ */
/* $NetBSD: trap.c,v 1.19 2003/03/13 13:44:20 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -487,15 +487,11 @@ trapa_panic:
void
panic_trap(struct trapframe *tf, register_t ssr, register_t spc,
register_t expevt, int extype)
register_t expevt)
{
struct exc_scratch_frame excf;
struct cpu_info *ci = curcpu();
register_t tlbregs[9];
register_t kcr0, kcr1;
asm volatile("getcon kcr0, %0" : "=r"(kcr0));
asm volatile("getcon kcr1, %0" : "=r"(kcr1));
excf = ci->ci_escratch;
tlbregs[0] = ci->ci_tscratch.ts_r[0];
@ -513,46 +509,21 @@ panic_trap(struct trapframe *tf, register_t ssr, register_t spc,
*/
ci->ci_escratch.es_critical = 0;
switch (extype) {
case 0:
printf("\n\nPANIC trap: %s in %s mode\n\n",
trap_type((int)expevt),
((ssr & SH5_CONREG_SR_MD) == 0) ? "user" : "kernel");
break;
case 1:
printf("\n\nDEBUG Synchronous Exception: %s in %s mode\n\n",
trap_type((int)tf->tf_state.sf_expevt),
USERMODE(tf) ? "user" : "kernel");
break;
case 2:
printf("\n\nDEBUG Interrupt Exception: 0x%x from %s mode\n\n",
(u_int)tf->tf_state.sf_intevt,
USERMODE(tf) ? "user" : "kernel");
break;
default:
printf("\n\nUnknown DEBUG exception %d from %s mode\n\n",
extype, USERMODE(tf) ? "user" : "kernel");
break;
}
printf("\n\nPANIC trap: %s in %s mode\n", trap_type((int)expevt),
USERMODE(tf) ? "user" : "kernel");
printf(
" SSR=0x%x, SPC=0x%lx, EXPEVT=0x%04x, TEA=0x%08lx, TRA=0x%x\n",
" SSR=0x%x, SPC=0x%lx, EXPEVT=0x%04x, TEA=0x%lx, TRA=0x%x\n",
(u_int)ssr, (uintptr_t)spc, (u_int)expevt,
(uintptr_t)tf->tf_state.sf_tea, (u_int)tf->tf_state.sf_tra);
if (extype == 0) {
printf("PSSR=0x%08x, PSPC=0x%lx, PEXPEVT=0x%04x\n",
(u_int)tf->tf_state.sf_ssr, (uintptr_t)tf->tf_state.sf_spc,
(u_int)tf->tf_state.sf_expevt);
tf->tf_state.sf_ssr = ssr;
tf->tf_state.sf_spc = spc;
tf->tf_state.sf_expevt = expevt;
}
printf("PSSR=0x%08x, PSPC=0x%lx, PEXPEVT=0x%04x\n",
(u_int)tf->tf_state.sf_ssr, (uintptr_t)tf->tf_state.sf_spc,
(u_int)tf->tf_state.sf_expevt);
printf("KCR0=0x%lx, KCR1=0x%lx\n\n", (intptr_t)kcr0, (intptr_t)kcr1);
tf->tf_state.sf_ssr = ssr;
tf->tf_state.sf_spc = spc;
tf->tf_state.sf_expevt = expevt;
printf("Exc Scratch Area:\n");
printf(" CRIT: 0x%x\n", (u_int)excf.es_critical);