matt d852904749 Add a KASSERT to make sure the counter is running.		2014-06-11 05:50:46 +00:00
..
a9_mpsubr.S	Fix wrong instruction; mrc => mcr	2014-05-21 01:02:45 +00:00
a9tmr_intr.h
a9tmr_reg.h
a9tmr_var.h	Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args.	2013-06-20 05:30:21 +00:00
a9tmr.c	Mark interrupt as MPSAFE.	2014-03-28 21:57:22 +00:00
a9wdt.c	write correct register.	2014-04-13 02:20:33 +00:00
armperiph.c	Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args.	2013-06-20 05:30:21 +00:00
cpu_in_cksum_asm_neon.S	Rework considerably. Use alternating sets of registers.	2012-12-22 18:58:29 +00:00
cpu_in_cksum_neon.c	Add preliminary version of a NEON based in_cksum routine.	2012-12-17 00:44:03 +00:00
files.cortex	Add needs-flag to arml2cc	2014-02-19 22:20:03 +00:00
gic_intr.h	add helper macros.	2014-04-09 16:59:53 +00:00
gic_reg.h	When dealing with the PMR register, only use non-secure priority values.	2014-04-27 16:22:13 +00:00
gic.c	Implement MI IPI interface with cross-call support.	2014-05-19 22:47:53 +00:00
gtmr_intr.h	Add generic timer support (untested)	2013-06-16 16:44:39 +00:00
gtmr_var.h	Add gtmr_bootdelay. rename clockhandler to gtmr_intr	2014-03-28 21:41:46 +00:00
gtmr.c	Add a KASSERT to make sure the counter is running.	2014-06-11 05:50:46 +00:00
mpcore_var.h	Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args.	2013-06-20 05:30:21 +00:00
pl310_reg.h	Add constant for a reserved bit 31 for the L2C_AUXCTL register for use in	2014-03-22 17:12:20 +00:00
pl310_var.h	Switch cortex_a9 back to need_ptesync = 1	2012-09-07 11:48:59 +00:00
pl310.c	Allow l2cc base to gotten from device properties.	2014-04-16 22:40:00 +00:00
scu_reg.h