0ae3de1a27
re-enabled with ASC_IOASIC_BOUNCE. All DMA buffered processing is now done in the bus-specific DMA routines in asc_ioasic.c and asc_tc.c. Disable several informational messages dealing with non-empty FIFO conditions, but allow enabling with ASC_DIAGNOSTIC for troubleshooting.
325 lines
8.5 KiB
C
325 lines
8.5 KiB
C
/* $NetBSD: asc_ioasic.c,v 1.11 1997/07/28 19:39:25 mhitch Exp $ */
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/*
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* Copyright 1996 The Board of Trustees of The Leland Stanford
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* Junior University. All Rights Reserved.
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*
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* Permission to use, copy, modify, and distribute this
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* software and its documentation for any purpose and without
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* fee is hereby granted, provided that the above copyright
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* notice appear in all copies. Stanford University
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* makes no representations about the suitability of this
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* software for any purpose. It is provided "as is" without
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* express or implied warranty.
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*
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*/
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#define USE_CACHED_BUFFER 0
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <dev/tc/tcvar.h>
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#include <dev/tc/ioasicvar.h>
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#include <machine/autoconf.h>
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#include <pmax/dev/device.h> /* XXX */
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#include <pmax/dev/scsi.h> /* XXX */
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#include <pmax/dev/ascreg.h> /* XXX */
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#include <dev/tc/ascvar.h>
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#include <machine/cpu.h>
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#include <machine/bus.h> /* bus, cache consistency, etc */
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/*XXX*/
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#include <pmax/pmax/asic.h> /* XXX ioasic register defs? */
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#include <pmax/pmax/kmin.h> /* XXX ioasic register defs? */
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#include <pmax/pmax/pmaxtype.h>
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extern int pmax_boardtype;
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extern vm_offset_t kvtophys __P((vm_offset_t));
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/*
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* Autoconfiguration data for config.
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*/
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int asc_ioasic_match __P((struct device *, struct cfdata *, void *));
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void asc_ioasic_attach __P((struct device *, struct device *, void *));
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struct cfattach asc_ioasic_ca = {
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sizeof(struct asc_softc), asc_ioasic_match, asc_ioasic_attach
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};
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/*
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* DMA callback declarations
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*/
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#ifdef ASC_IOASIC_BOUNCE
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extern u_long asc_iomem;
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#endif
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static int
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asic_dma_start __P((asc_softc_t asc, State *state, caddr_t cp, int flag,
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int len, int off));
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static void
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asic_dma_end __P((asc_softc_t asc, State *state, int flag));
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int
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asc_ioasic_match(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct ioasicdev_attach_args *d = aux;
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void *ascaddr;
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if (strncmp(d->iada_modname, "asc", TC_ROM_LLEN) &&
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strncmp(d->iada_modname, "PMAZ-AA ", TC_ROM_LLEN))
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return (0);
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/* probe for chip */
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ascaddr = (void*)d->iada_addr;
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if (tc_badaddr(ascaddr + ASC_OFFSET_53C94))
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return (0);
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return (1);
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}
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void
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asc_ioasic_attach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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register struct ioasicdev_attach_args *d = aux;
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register asc_softc_t asc = (asc_softc_t) self;
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#ifdef ASC_IOASIC_BOUNCE
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u_char *buff;
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int i;
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#endif
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void *ascaddr;
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int unit;
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ascaddr = (void*)MIPS_PHYS_TO_KSEG1(d->iada_addr);
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unit = asc->sc_dev.dv_unit;
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/*
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* Initialize hw descriptor, cache some pointers
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*/
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asc->regs = (asc_regmap_t *)(ascaddr + ASC_OFFSET_53C94);
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/*
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* Set up machine dependencies.
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* (1) how to do dma
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* (2) timing based on turbochannel frequency
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*/
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#ifdef ASC_IOASIC_BOUNCE
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#if USE_CACHED_BUFFER
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/* XXX Use cached address for DMA buffer to increase raw read speed */
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buff = (u_char *)MIPS_PHYS_TO_KSEG0(asc_iomem);
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#else
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buff = (u_char *)MIPS_PHYS_TO_KSEG1(asc_iomem);
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#endif /* USE_CACHED_BUFFER */
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/*
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* Statically partition the DMA buffer between targets.
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* This way we will eventually be able to attach/detach
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* drives on-fly. And 18k/target is plenty for normal use.
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*/
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/*
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* Give each target its own DMA buffer region.
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* We may want to try ping ponging buffers later.
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*/
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for (i = 0; i < ASC_NCMD; i++)
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asc->st[i].dmaBufAddr = buff + 8192 * i;
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#endif /* ASC_IOASIC_BOUNCE */
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*((volatile int *)IOASIC_REG_SCSI_DMAPTR(ioasic_base)) = -1;
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*((volatile int *)IOASIC_REG_SCSI_DMANPTR(ioasic_base)) = -1;
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*((volatile int *)IOASIC_REG_SCSI_SCR(ioasic_base)) = 0;
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asc->dma_start = asic_dma_start;
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asc->dma_end = asic_dma_end;
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/* digital meters show IOASIC 53c94s are clocked at approx 25MHz */
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ascattach(asc, ASC_SPEED_25_MHZ);
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/* tie pseudo-slot to device */
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ioasic_intr_establish(parent, d->iada_cookie, TC_IPL_BIO,
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asc_intr, asc);
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}
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/*
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* DMA handling routines. For a turbochannel device, just set the dmar.
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* For the I/O ASIC, handle the actual DMA interface.
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*/
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static int
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asic_dma_start(asc, state, cp, flag, len, off)
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asc_softc_t asc;
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State *state;
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caddr_t cp;
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int flag;
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int len;
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int off;
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{
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register volatile u_int *ssr = (volatile u_int *)
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IOASIC_REG_CSR(ioasic_base);
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u_int phys, nphys;
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/* stop DMA engine first */
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*ssr &= ~IOASIC_CSR_DMAEN_SCSI;
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*((volatile int *)IOASIC_REG_SCSI_SCR(ioasic_base)) = 0;
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#ifndef ASC_IOASIC_BOUNCE
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/* restrict len to the maximum the IOASIC can transfer */
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if (len > ((caddr_t)mips_trunc_page(cp + NBPG * 2) - cp))
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len = (caddr_t)mips_trunc_page(cp + NBPG * 2) - cp;
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/* If R4K, writeback and invalidate the buffer */
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if (CPUISMIPS3)
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mips3_HitFlushDCache((vm_offset_t)cp, len);
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/* Get physical address of buffer start, no next phys addr */
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phys = (u_int)kvtophys((vm_offset_t)cp);
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nphys = -1;
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/* Compute 2nd DMA pointer only if next page is part of this I/O */
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if ((NBPG - (phys & (NBPG - 1))) < len) {
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cp = (caddr_t)mips_trunc_page(cp + NBPG);
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nphys = (u_int)kvtophys((vm_offset_t)cp);
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}
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/* If not R4K, need to invalidate cache lines for both physical segments */
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if (!CPUISMIPS3 && flag == ASCDMA_READ) {
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MachFlushDCache(MIPS_PHYS_TO_KSEG0(phys),
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nphys == 0xffffffff ? len : NBPG - (phys & (NBPG - 1)));
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if (nphys != 0xffffffff)
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MachFlushDCache(MIPS_PHYS_TO_KSEG0(nphys),
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NBPG); /* XXX */
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}
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#else /* ASC_IOASIC_BOUNCE */
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/* restrict len to the maximum the IOASIC can transfer */
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if (len > ((caddr_t)mips_trunc_page(state->dmaBufAddr + off + NBPG * 2) - (caddr_t)(state->dmaBufAddr + off)))
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len = (caddr_t)mips_trunc_page(state->dmaBufAddr + off + NBPG * 2) - (caddr_t)(state->dmaBufAddr + off);
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if (flag == ASCDMA_WRITE)
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bcopy(cp, state->dmaBufAddr + off, len);
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cp = state->dmaBufAddr + off;
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#if USE_CACHED_BUFFER
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#ifdef MIPS3
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/* If R4K, need to writeback the bounce buffer */
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if (CPUISMIPS3)
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mips3_HitFlushDCache((vm_offset_t)cp, len);
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#endif /* MIPS3 */
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phys = MIPS_KSEG0_TO_PHYS(cp);
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cp = (caddr_t)mips_trunc_page(cp + NBPG);
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nphys = MIPS_KSEG0_TO_PHYS(cp);
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#else
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phys = MIPS_KSEG1_TO_PHYS(cp);
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cp = (caddr_t)mips_trunc_page(cp + NBPG);
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nphys = MIPS_KSEG1_TO_PHYS(cp);
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#endif /* USE_CACHED_BUFFER */
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#endif /* ASC_IOASIC_BOUNCE */
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#ifdef notyet
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asc->dma_next = cp;
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asc->dma_xfer = state->dmalen - (nphys - phys);
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#endif
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*(volatile int *)IOASIC_REG_SCSI_DMAPTR(ioasic_base) =
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IOASIC_DMA_ADDR(phys);
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*(volatile int *)IOASIC_REG_SCSI_DMANPTR(ioasic_base) =
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IOASIC_DMA_ADDR(nphys);
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if (flag == ASCDMA_READ)
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*ssr |= IOASIC_CSR_SCSI_DIR | IOASIC_CSR_DMAEN_SCSI;
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else
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*ssr = (*ssr & ~IOASIC_CSR_SCSI_DIR) | IOASIC_CSR_DMAEN_SCSI;
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wbflush();
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return (len);
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}
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static void
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asic_dma_end(asc, state, flag)
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asc_softc_t asc;
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State *state;
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int flag;
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{
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register volatile u_int *ssr = (volatile u_int *)
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IOASIC_REG_CSR(ioasic_base);
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register volatile u_int *dmap = (volatile u_int *)
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IOASIC_REG_SCSI_DMAPTR(ioasic_base);
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register u_short *to;
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register int w;
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int nb;
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*ssr &= ~IOASIC_CSR_DMAEN_SCSI;
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#if USE_CACHED_BUFFER /* XXX - Should uncached address always be used? */
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to = (u_short *)MIPS_PHYS_TO_KSEG0(*dmap >> 3);
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#else
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to = (u_short *)MIPS_PHYS_TO_KSEG1(*dmap >> 3);
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#endif
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*dmap = -1;
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*((volatile int *)IOASIC_REG_SCSI_DMANPTR(ioasic_base)) = -1;
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wbflush();
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if (flag == ASCDMA_READ) {
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#if !defined(ASC_IOASIC_BOUNCE) && USE_CACHED_BUFFER
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/* Invalidate cache for the buffer */
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#ifdef MIPS3
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if (CPUISMIPS3)
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MachFlushDCache(MIPS_KSEG1_TO_PHYS(state->dmaBufAddr),
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state->dmalen);
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else
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#endif /* MIPS3 */
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MachFlushDCache(MIPS_PHYS_TO_KSEG0(
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MIPS_KSEG1_TO_PHYS(state->dmaBufAddr)),
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state->dmalen);
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#endif /* USE_CACHED_BUFFER */
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if ( (nb = *((int *)IOASIC_REG_SCSI_SCR(ioasic_base))) != 0) {
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/* pick up last upto6 bytes, sigh. */
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/* Last byte really xferred is.. */
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w = *(int *)IOASIC_REG_SCSI_SDR0(ioasic_base);
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*to++ = w;
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if (--nb > 0) {
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w >>= 16;
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*to++ = w;
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}
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if (--nb > 0) {
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w = *(int *)IOASIC_REG_SCSI_SDR1(ioasic_base);
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*to++ = w;
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}
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}
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#ifdef ASC_IOASIC_BOUNCE
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bcopy(state->dmaBufAddr, state->buf, state->dmalen);
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#endif
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}
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}
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#ifdef notdef
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/*
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* Called by asic_intr() for scsi dma pointer update interrupts.
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*/
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void
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asc_dma_intr()
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{
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asc_softc_t asc = &asc_cd.cd_devs[0]; /*XXX*/
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u_int next_phys;
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asc->dma_xfer -= NBPG;
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if (asc->dma_xfer <= -NBPG) {
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volatile u_int *ssr = (volatile u_int *)
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IOASIC_REG_CSR(ioasic_base);
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*ssr &= ~IOASIC_CSR_DMAEN_SCSI;
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} else {
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asc->dma_next += NBPG;
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next_phys = MIPS_KSEG0_TO_PHYS(asc->dma_next);
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}
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*(volatile int *)IOASIC_REG_SCSI_DMANPTR(ioasic_base) =
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IOASIC_DMA_ADDR(next_phys);
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wbflush();
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}
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#endif /*notdef*/
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