527 lines
14 KiB
C
527 lines
14 KiB
C
/* $NetBSD: pq3gpio.c,v 1.8 2012/07/15 08:44:56 matt Exp $ */
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/*-
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* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Raytheon BBN Technologies Corp and Defense Advanced Research Projects
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* Agency and which was developed by Matt Thomas of 3am Software Foundry.
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*
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* This material is based upon work supported by the Defense Advanced Research
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* Projects Agency and Space and Naval Warfare Systems Center, Pacific, under
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* Contract No. N66001-09-C-2073.
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* Approved for Public Release, Distribution Unlimited
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#define GLOBAL_PRIVATE
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#define GPIO_PRIVATE
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#include "opt_mpc85xx.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pq3gpio.c,v 1.8 2012/07/15 08:44:56 matt Exp $");
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#include <sys/param.h>
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#include <sys/cpu.h>
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#include <sys/device.h>
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#include <sys/tty.h>
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#include <sys/kmem.h>
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#include <sys/gpio.h>
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#include <sys/bitops.h>
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#include "ioconf.h"
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#include <sys/intr.h>
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#include <sys/bus.h>
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#include <dev/gpio/gpiovar.h>
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#include <powerpc/booke/cpuvar.h>
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#include <powerpc/booke/spr.h>
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#include <powerpc/booke/e500var.h>
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#include <powerpc/booke/e500reg.h>
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struct pq3gpio_group {
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struct gpio_chipset_tag gc_tag;
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gpio_pin_t gc_pins[32];
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bus_space_tag_t gc_bst;
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bus_space_handle_t gc_bsh;
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bus_size_t gc_reg;
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};
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struct pq3gpio_softc {
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device_t sc_dev;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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SIMPLEQ_HEAD(,pq3gpio_group) sc_gpios;
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};
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static int
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pq3gpio_pin_read(void *v, int num)
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{
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struct pq3gpio_group * const gc = v;
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uint32_t data = bus_space_read_4(gc->gc_bst, gc->gc_bsh, gc->gc_reg);
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return (data >> (gc->gc_pins[num].pin_num ^ 31)) & 1;
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}
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static void
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pq3gpio_pin_write(void *v, int num, int val)
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{
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struct pq3gpio_group * const gc = v;
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const u_int mask = 1 << (gc->gc_pins[num].pin_num ^ 31);
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val = val ? mask : 0;
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u_int data = bus_space_read_4(gc->gc_bst, gc->gc_bsh, gc->gc_reg);
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if ((data & mask) != val) {
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data = (data & ~mask) | val;
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bus_space_write_4(gc->gc_bst, gc->gc_bsh, gc->gc_reg, data);
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}
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}
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#if defined(MPC8548) || defined(MPC8555) || defined(MPC8544)
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static void
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pq3gpio_null_pin_ctl(void *v, int num, int ctl)
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{
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}
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#endif
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#if defined(P1025)
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/*
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* P1025 has controllable input/output pins
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*/
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static void
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pq3gpio_pin_ctl(void *v, int num, int ctl)
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{
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struct pq3gpio_group * const gc = v;
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const size_t shift = gc->gc_pins[num].pin_num ^ 31;
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uint64_t old_dir =
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((uint64_t)bus_space_read_4(gc->gc_bst, gc->gc_bsh, CPDIR1) << 32)
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| (bus_space_read_4(gc->gc_bst, gc->gc_bsh, CPDIR2) << 0);
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uint32_t dir = 0;
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switch (ctl & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
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case GPIO_PIN_INPUT|GPIO_PIN_OUTPUT: dir = CPDIR_INOUT; break;
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case GPIO_PIN_OUTPUT: dir = CPDIR_OUT; break;
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case GPIO_PIN_INPUT: dir = CPDIR_INOUT; break;
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case 0: dir = CPDIR_DIS; break;
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}
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uint64_t new_dir = (old_dir & (3ULL << (2 * shift)))
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| ((uint64_t)dir << (2 * shift));
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if ((uint32_t)old_dir != (uint32_t)new_dir)
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bus_space_write_4(gc->gc_bst, gc->gc_bsh, CPDIR2,
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(uint32_t)new_dir);
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new_dir >>= 32;
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old_dir >>= 32;
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if ((uint32_t)old_dir != (uint32_t)new_dir)
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bus_space_write_4(gc->gc_bst, gc->gc_bsh, CPDIR1,
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(uint32_t)new_dir);
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/*
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* Now handle opendrain
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*/
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uint32_t old_odr = bus_space_read_4(gc->gc_bst, gc->gc_bsh, CPODR);
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uint32_t new_odr = old_odr;
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uint32_t odr_mask = 1UL << shift;
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if (ctl & GPIO_PIN_OPENDRAIN) {
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new_odr |= odr_mask;
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} else {
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new_odr &= ~odr_mask;
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}
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if (old_odr != new_odr)
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bus_space_write_4(gc->gc_bst, gc->gc_bsh, CPODR, new_odr);
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}
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#endif
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#if defined(MPC8536) || defined(P2020)
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/*
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* MPC8536 / P20x0 have controllable input/output pins
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*/
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static void
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pq3gpio_pin_ctl(void *v, int num, int ctl)
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{
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struct pq3gpio_group * const gc = v;
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const u_int mask = 1 << (gc->gc_pins[num].pin_num ^ 31);
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uint32_t old_dir = bus_space_read_4(gc->gc_bst, gc->gc_bsh, GPDIR);
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uint32_t new_dir = old_dir;
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switch (ctl & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
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case GPIO_PIN_OUTPUT: new_dir |= mask; break;
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case GPIO_PIN_INPUT: new_dir &= ~mask; break;
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default: return;
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}
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if (old_dir != new_dir)
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bus_space_write_4(gc->gc_bst, gc->gc_bsh, GPDIR, new_dir);
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/*
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* Now handle opendrain
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*/
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uint32_t old_odr = bus_space_read_4(gc->gc_bst, gc->gc_bsh, GPODR);
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uint32_t new_odr = old_odr;
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if (ctl & GPIO_PIN_OPENDRAIN) {
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new_odr |= mask;
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} else {
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new_odr &= ~mask;
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}
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if (old_odr != new_odr)
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bus_space_write_4(gc->gc_bst, gc->gc_bsh, GPODR, new_odr);
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}
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#endif
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static void
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pq3gpio_group_create(device_t self, bus_space_tag_t bst, bus_space_handle_t bsh,
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bus_size_t reg, uint32_t pinmask, int pincaps,
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void (*pin_ctl)(void *, int, int))
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{
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struct pq3gpio_group * const gc = kmem_zalloc(sizeof(*gc), KM_SLEEP);
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gc->gc_bst = bst;
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gc->gc_bsh = bsh;
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gc->gc_reg = reg;
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gc->gc_tag.gp_cookie = gc;
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#if 0
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gc->gc_tag.gp_gc_open = pq3gpio_gc_open;
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gc->gc_tag.gp_gc_close = pq3gpio_gc_close;
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#endif
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gc->gc_tag.gp_pin_read = pq3gpio_pin_read;
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gc->gc_tag.gp_pin_write = pq3gpio_pin_write;
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gc->gc_tag.gp_pin_ctl = pin_ctl;
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u_int data = bus_space_read_4(gc->gc_bst, gc->gc_bsh, reg);
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u_int mask = __BIT(31);
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gpio_pin_t *pin = gc->gc_pins;
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for (u_int i = 0; mask != 0; i++, mask >>= 1) {
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if (mask & pinmask) {
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pin->pin_num = i;
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pin->pin_caps = pincaps;
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pin->pin_flags = pincaps;
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pin->pin_state = (data & mask) != 0;
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pin++;
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}
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}
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struct gpiobus_attach_args gba = {
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.gba_gc = &gc->gc_tag,
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.gba_pins = gc->gc_pins,
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.gba_npins = pin - gc->gc_pins,
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};
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config_found_ia(self, "gpiobus", &gba, gpiobus_print);
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}
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#ifdef MPC8536
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static void
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pq3gpio_mpc8536_attach(device_t self, bus_space_tag_t bst,
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bus_space_handle_t bsh, u_int svr)
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{
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static const uint8_t gpio2pmuxcr_map[] = {
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[0] = ilog2(PMUXCR_PCI_REQGNT3),
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[1] = ilog2(PMUXCR_PCI_REQGNT4),
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[2] = ilog2(PMUXCR_PCI_REQGNT3),
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[3] = ilog2(PMUXCR_PCI_REQGNT4),
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[4] = ilog2(PMUXCR_SDHC_CD),
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[5] = ilog2(PMUXCR_SDHC_WP),
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[6] = ilog2(PMUXCR_USB1),
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[7] = ilog2(PMUXCR_USB1),
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[8] = ilog2(PMUXCR_USB2),
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[9] = ilog2(PMUXCR_USB2),
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[10] = ilog2(PMUXCR_DMA0),
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[11] = ilog2(PMUXCR_DMA1),
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[12] = ilog2(PMUXCR_DMA0),
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[13] = ilog2(PMUXCR_DMA1),
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[14] = ilog2(PMUXCR_DMA0),
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[15] = ilog2(PMUXCR_DMA1),
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};
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uint32_t pinmask = 0xffff0000; /* assume all bits are valid */
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uint32_t gpiomask = __BIT(31);
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size_t pincnt = 16;
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const uint32_t pmuxcr = cpu_read_4(GLOBAL_BASE + PMUXCR);
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for (size_t i = 0; i < __arraycount(gpio2pmuxcr_map);
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i++, gpiomask >>= 1) {
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if (pmuxcr & __BIT(gpio2pmuxcr_map[i])) {
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pinmask &= ~gpiomask;
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pincnt--;
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}
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}
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/*
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* Create GPIO pin groups
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*/
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aprint_normal_dev(self, "%zu input/output/opendrain pins\n",
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pincnt);
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pq3gpio_group_create(self, bst, bsh, GPDAT, pinmask,
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GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN,
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pq3gpio_pin_ctl);
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}
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#endif /* MPC8536 */
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#ifdef MPC8544
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static void
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pq3gpio_mpc8544_attach(device_t self, bus_space_tag_t bst,
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bus_space_handle_t bsh, u_int svr)
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{
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/*
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* Enable GPOUT
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*/
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uint32_t gpiocr = bus_space_read_4(bst, bsh, GPIOCR);
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gpiocr |= GPIOCR_GPOUT;
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bus_space_write_4(bst, bsh, GPIOCR, gpiocr);
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aprint_normal_dev(self, "8 input pins, 8 output pins\n");
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/*
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* Create GPIO pin groups
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*/
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pq3gpio_group_create(self, bst, bsh, GPINDR, 0xff000000,
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GPIO_PIN_INPUT, pq3gpio_null_pin_ctl);
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pq3gpio_group_create(self, bst, bsh, GPOUTDR, 0xff000000,
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GPIO_PIN_OUTPUT, pq3gpio_null_pin_ctl);
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}
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#endif /* MPC8544 */
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#if defined(MPC8548) || defined(MPC8555)
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static void
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pq3gpio_mpc8548_attach(device_t self, bus_space_tag_t bst,
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bus_space_handle_t bsh, u_int svr)
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{
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const uint32_t pordevsr = bus_space_read_4(bst, bsh, PORDEVSR);
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const uint32_t devdisr = bus_space_read_4(bst, bsh, DEVDISR);
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uint32_t gpiocr = bus_space_read_4(bst, bsh, GPIOCR);
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uint32_t inmask = 0;
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uint32_t outmask = 0;
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size_t ipins = 0;
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size_t opins = 0;
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aprint_normal_dev(self, "GPIOCR %#x, DEVDISR %#x, PORDEVSR %#x\n",
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gpiocr, devdisr, pordevsr);
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aprint_normal_dev(self, "GPINDR %#x, GPOUTDR %#x, GPPORCR %#x\n",
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bus_space_read_4(bst, bsh, GPINDR),
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bus_space_read_4(bst, bsh, GPOUTDR),
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bus_space_read_4(bst, bsh, GPPORCR));
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/*
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* Use PCI2 AD[15:0] as GPIO if PCI2 is disabled and
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* PCI1 is either disabled or not 64bits wide.
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*/
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if ((devdisr & DEVDISR_PCI2) &&
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((devdisr & DEVDISR_PCI1) || (pordevsr & PORDEVSR_PCI32))) {
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gpiocr |= GPIOCR_PCIOUT;
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gpiocr |= GPIOCR_PCIIN;
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outmask |= 0x00ff0000;
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inmask |= 0x00ff0000;
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opins += 8;
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ipins += 8;
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}
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if (devdisr & DEVDISR_TSEC2) {
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gpiocr |= GPIOCR_TX2;
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gpiocr |= GPIOCR_RX2;
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outmask |= 0xff000000;
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inmask |= 0xff000000;
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opins += 8;
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ipins += 8;
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}
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if (svr != (SVR_MPC8555v1 >> 16)) {
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gpiocr |= GPIOCR_GPOUT;
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outmask |= 0x000000ff;
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opins += 8;
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}
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#if 1
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aprint_normal_dev(self, "GPIOCR: %#x\n", gpiocr);
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#else
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bus_space_write_4(bst, bsh, GPIOCR, gpiocr);
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#endif
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/*
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* Create GPIO pin groups
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*/
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aprint_normal_dev(self, "%zu input pins, %zu output pins\n",
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ipins, opins);
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if (inmask)
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pq3gpio_group_create(self, bst, bsh, GPINDR, inmask,
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GPIO_PIN_INPUT, pq3gpio_null_pin_ctl);
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if (outmask)
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pq3gpio_group_create(self, bst, bsh, GPOUTDR, outmask,
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GPIO_PIN_OUTPUT, pq3gpio_null_pin_ctl);
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}
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#endif /* MPC8548 */
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#ifdef P1025
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static void
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pq3gpio_p1025_attach(device_t self, bus_space_tag_t bst,
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bus_space_handle_t bsh, u_int svr)
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{
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static const uint32_t gpio2pmuxcr_map[][4] = {
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{ 0, __BIT(12), 0, PMUXCR_SDHC_WP },
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{ __BIT(15), __BIT(8), 0, PMUXCR_USB1 },
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{ __BITS(14,4)|__BIT(16)|__BITS(27,17)|__BIT(30),
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__BIT(1)|__BITS(3,2), 0, PMUXCR_QE0 },
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{ __BITS(3,1), 0, 0, PMUXCR_QE3 },
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{ 0, __BITS(17,14), 0, PMUXCR_QE8 },
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{ __BIT(29), __BITS(19,18), 0, PMUXCR_QE9 },
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{ 0, __BITS(22,21), 0, PMUXCR_QE10 },
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{ 0, __BITS(28,23), 0, PMUXCR_QE11 },
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{ 0, __BIT(20), 0, PMUXCR_QE12 },
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};
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uint32_t pinmask[3] = {
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0xffffffff, 0xffffffff, 0xffffffff
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}; /* assume all bits are valid */
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const uint32_t pmuxcr = cpu_read_4(GLOBAL_BASE + PMUXCR);
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for (size_t i = 0; i < __arraycount(gpio2pmuxcr_map); i++) {
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if (pmuxcr & gpio2pmuxcr_map[i][3]) {
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pinmask[0] &= ~gpio2pmuxcr_map[i][0];
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pinmask[1] &= ~gpio2pmuxcr_map[i][1];
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pinmask[2] &= ~gpio2pmuxcr_map[i][2];
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}
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}
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/*
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* Create GPIO pin groups
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*/
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for (size_t i = 0; i < 3; i++) {
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if (pinmask[i]) {
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bus_space_handle_t bsh2;
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aprint_normal_dev(self,
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"gpio[%c]: %zu input/output/opendrain pins\n",
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"abc"[i], popcount32(pinmask[i]));
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bus_space_subregion(bst, bsh, CPBASE(i), 0x20, &bsh2);
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pq3gpio_group_create(self, bst, bsh2, CPDAT,
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pinmask[0],
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GPIO_PIN_INPUT|GPIO_PIN_OUTPUT|GPIO_PIN_OPENDRAIN,
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pq3gpio_pin_ctl);
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}
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}
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}
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#endif /* P1025 */
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#ifdef P2020
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static void
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pq3gpio_p20x0_attach(device_t self, bus_space_tag_t bst,
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bus_space_handle_t bsh, u_int svr)
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{
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static const uint32_t gpio2pmuxcr_map[][2] = {
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{ __BIT(8), PMUXCR_SDHC_CD },
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{ __BIT(9), PMUXCR_SDHC_WP },
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/*
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* These are really two bits but the low bit MBZ so we ignore
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* it.
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*/
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{ __BIT(10), PMUXCR_TSEC3_TS },
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{ __BIT(11), PMUXCR_TSEC3_TS },
|
|
};
|
|
|
|
uint32_t pinmask = 0xffff0000; /* assume all bits are valid */
|
|
size_t pincnt = 16;
|
|
const uint32_t pmuxcr = cpu_read_4(GLOBAL_BASE + PMUXCR);
|
|
for (size_t i = 0; i < __arraycount(gpio2pmuxcr_map); i++) {
|
|
if (pmuxcr & gpio2pmuxcr_map[i][1]) {
|
|
pinmask &= ~gpio2pmuxcr_map[i][0];
|
|
pincnt--;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Create GPIO pin groups
|
|
*/
|
|
aprint_normal_dev(self, "%zu input/output/opendrain pins\n",
|
|
pincnt);
|
|
pq3gpio_group_create(self, bst, bsh, GPDAT, pinmask,
|
|
GPIO_PIN_INPUT|GPIO_PIN_OUTPUT|GPIO_PIN_OPENDRAIN,
|
|
pq3gpio_pin_ctl);
|
|
}
|
|
#endif /* P2020 */
|
|
|
|
static const struct pq3gpio_svr_info {
|
|
uint16_t si_svr;
|
|
void (*si_attach)(device_t, bus_space_tag_t, bus_space_handle_t, u_int);
|
|
bus_addr_t si_base;
|
|
bus_size_t si_size;
|
|
} pq3gpio_svrs[] = {
|
|
#ifdef MPC8548
|
|
{ SVR_MPC8548v2 >> 16, pq3gpio_mpc8548_attach,
|
|
GLOBAL_BASE, GLOBAL_SIZE },
|
|
#endif
|
|
#ifdef MPC8555
|
|
{ SVR_MPC8555v1 >> 16, pq3gpio_mpc8548_attach,
|
|
GLOBAL_BASE, GLOBAL_SIZE },
|
|
#endif
|
|
#ifdef MPC8544
|
|
{ SVR_MPC8544v1 >> 16, pq3gpio_mpc8544_attach,
|
|
GLOBAL_BASE, GLOBAL_SIZE },
|
|
#endif
|
|
#ifdef MPC8536
|
|
{ SVR_MPC8536v1 >> 16, pq3gpio_mpc8536_attach,
|
|
GPIO_BASE, GPIO_SIZE },
|
|
#endif
|
|
#ifdef P1025
|
|
{ SVR_P1025v1 >> 16, pq3gpio_p1025_attach,
|
|
GLOBAL_BASE, GLOBAL_SIZE },
|
|
#endif
|
|
#ifdef P2020
|
|
{ SVR_P2020v2 >> 16, pq3gpio_p20x0_attach,
|
|
GPIO_BASE, GPIO_SIZE },
|
|
#endif
|
|
};
|
|
|
|
void
|
|
pq3gpio_attach(device_t parent, device_t self, void *aux)
|
|
{
|
|
struct mainbus_attach_args * const ma = aux;
|
|
bus_space_tag_t bst = ma->ma_memt;
|
|
bus_space_handle_t bsh;
|
|
|
|
const uint16_t svr = e500_get_svr();
|
|
for (u_int i = 0; i < __arraycount(pq3gpio_svrs); i++) {
|
|
const struct pq3gpio_svr_info * const si = &pq3gpio_svrs[i];
|
|
if (si->si_svr == svr) {
|
|
int error = bus_space_map(bst, si->si_base,
|
|
si->si_size, 0, &bsh);
|
|
if (error) {
|
|
aprint_error_dev(self,
|
|
"can't map global registers for gpio: %d\n",
|
|
error);
|
|
return;
|
|
}
|
|
(*si->si_attach)(self, bst, bsh, svr);
|
|
return;
|
|
}
|
|
}
|
|
aprint_normal_dev(self,
|
|
"0 input groups, 0 output groups (unknown svr %#x)\n",
|
|
svr);
|
|
}
|