Add support for the Freescale TWR-P1025 evaluation board and the P1025/P1016
QorIQ processors. XXX tsec isn't working yet on the TWR-P1025.
This commit is contained in:
matt
parent
c154c1f08c
commit
a8a82a563c
10
sys/arch/evbppc/conf/INSTALL_TWRP1025
Normal file
10
sys/arch/evbppc/conf/INSTALL_TWRP1025
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@ -0,0 +1,10 @@
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# $NetBSD: INSTALL_TWRP1025,v 1.1 2012/07/15 08:44:56 matt Exp $
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include "arch/evbppc/conf/TWRP1025"
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#ident "INSTALL_P2020RDB-$Revision: 1.1 $"
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include "arch/evbppc/conf/INSTALL.inc"
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no config netbsd-sd0a
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no config nfsnetbsd
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9
sys/arch/evbppc/conf/INSTALL_TWRP1025.MP
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9
sys/arch/evbppc/conf/INSTALL_TWRP1025.MP
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@ -0,0 +1,9 @@
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# $NetBSD: INSTALL_TWRP1025.MP,v 1.1 2012/07/15 08:44:56 matt Exp $
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include "arch/evbppc/conf/TWRP1205.MP"
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#ident "INSTALL_TWRP1205.MP-$Revision: 1.1 $"
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include "arch/evbppc/conf/INSTALL.inc"
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no config nfsnetbsd
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224
sys/arch/evbppc/conf/TWRP1025
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224
sys/arch/evbppc/conf/TWRP1025
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@ -0,0 +1,224 @@
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# $NetBSD: TWRP1025,v 1.1 2012/07/15 08:44:56 matt Exp $
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#
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# TWRP1025 -- everything that's currently supported
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#
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include "arch/evbppc/conf/std.mpc85xx"
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options INCLUDE_CONFIG_FILE # embed config file in kernel binary
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ident "TWRP1025-$Revision: 1.1 $"
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maxusers 32
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makeoptions NEED_BINARY="yes"
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makeoptions NEED_UBOOTIMAGE="yes"
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#options UVMHIST
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#options UVMHIST_PRINT
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options P1025
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options SYS_CLK=66666667
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#options HZ=1000
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#options SDHC_DEBUG
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#options INSECURE # disable kernel security levels
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#options NTP # NTP phase/frequency locked loop
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options KTRACE # system call tracing via ktrace(1)
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options SYSVMSG # System V message queues
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options SYSVSEM # System V semaphores
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options SYSVSHM # System V shared memory
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options USERCONF # userconf(4) support
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#options PIPE_SOCKETPAIR # smaller, but slower pipe(2)
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#options SYSCTL_INCLUDE_DESCR # Include sysctl descriptions in kernel
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# Diagnostic/debugging support options
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options DIAGNOSTIC # cheap kernel consistency checks
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options DEBUG # expensive debugging checks/support
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#options SYSCALL_DEBUG # syscall debugging
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options DDB # in-kernel debugger
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options DDB_HISTORY_SIZE=512 # enable history editing in DDB
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options TRAP_PANICWAIT
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options SYMTAB_SPACE=410000 # size for embedded symbol table
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makeoptions DEBUG="-g" # compile full symbol table
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# Compatibility options
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#options COMPAT_09 # NetBSD 0.9,
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#options COMPAT_10 # NetBSD 1.0,
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#options COMPAT_11 # NetBSD 1.1,
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#options COMPAT_12 # NetBSD 1.2,
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options COMPAT_13 # NetBSD 1.3,
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options COMPAT_14 # NetBSD 1.4,
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options COMPAT_15 # NetBSD 1.5,
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options COMPAT_16 # NetBSD 1.6,
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options COMPAT_20 # NetBSD 2.0,
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options COMPAT_30 # NetBSD 3.0,
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options COMPAT_40 # NetBSD 4.0,
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options COMPAT_50 # NetBSD 5.0 compatibility.
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options COMPAT_43 # and 4.3BSD
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#options COMPAT_386BSD_MBRPART # recognize old partition ID
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#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
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options COMPAT_BSDPTY # /dev/[pt]ty?? ptys.
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# File systems
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file-system FFS # UFS
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file-system EXT2FS # second extended file system (linux)
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file-system LFS # log-structured file system
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file-system MFS # memory file system
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file-system NFS # Network File System client
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file-system CD9660 # ISO 9660 + Rock Ridge file system
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file-system MSDOSFS # MS-DOS file system
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#file-system FDESC # /dev/fd
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file-system TMPFS # efficient memory file system
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file-system KERNFS # /kern
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file-system NULLFS # loopback file system
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#file-system OVERLAY # overlay file system
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#file-system PUFFS # Userspace file systems (e.g. ntfs-3g & sshfs)
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file-system PROCFS # /proc
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#file-system UMAPFS # NULLFS + uid and gid remapping
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#file-system UNION # union file system
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file-system PTYFS # /dev/pts/N support
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# File system options
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options QUOTA # legacy UFS quotas
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options QUOTA2 # new, in-filesystem UFS quotas
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options FFS_EI # FFS Endian Independent support
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options WAPBL # File system journaling support
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options NFSSERVER # Network File System server
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#options FFS_NO_SNAPSHOT # No FFS snapshot support
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options EXT2FS_SYSTEM_FLAGS # makes ext2fs file flags (append and
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# immutable) behave as system flags.
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options NFS_BOOT_DHCP # Support DHCP NFS root
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# Networking options
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#options GATEWAY # packet forwarding
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options INET # IP + ICMP + TCP + UDP
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options INET_CSUM_COUNTERS
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options TCP_CSUM_COUNTERS
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options UDP_CSUM_COUNTERS
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#options INET6 # IPV6
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#options IPSEC # IP security
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#options IPSEC_ESP # IP security (encryption part; define w/IPSEC)
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#options IPSEC_NAT_T # IPsec NAT traversal (NAT-T)
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#options IPSEC_DEBUG # debug for IP security
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#options MROUTING # IP multicast routing
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#options PIM # Protocol Independent Multicast
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#options DIRECTED_BROADCAST # allow broadcasts through routers
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#options ISO,TPIP # OSI
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#options EON # OSI tunneling over IP
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#options NETATALK # AppleTalk networking protocols
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#options PPP_BSDCOMP # BSD-Compress compression support for PPP
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#options PPP_DEFLATE # Deflate compression support for PPP
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#options PPP_FILTER # Active filter support for PPP (requires bpf)
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#options PFIL_HOOKS # pfil(9) packet filter hooks
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#options IPFILTER_LOG # ipmon(8) log support
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#options IPFILTER_LOOKUP # ippool(8) support
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#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
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# These options enable verbose messages for several subsystems.
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# Warning, these may compile large string tables into the kernel!
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options PCIVERBOSE # verbose PCI device autoconfig messages
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options MIIVERBOSE # verbose PHY autoconfig messages
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#options PCI_CONFIG_DUMP # verbosely dump PCI config space
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options SCSIVERBOSE # human readable SCSI error messages
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#options PCI_NETBSD_CONFIGURE # Do not rely on BIOS/whatever to configure PCI devices
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#options PCI_CONFIGURE_VERBOSE # Show PCI config information
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# wscons options
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#options WSEMUL_SUN # sun terminal emulation
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#options WSEMUL_VT100 # VT100 / VT220 emulation
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# Kernel root file system and dump configuration.
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config netbsd root on ? type ?
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config netbsd-sd0a root on sd0a type ffs
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config nfsnetbsd root on tsec0 type nfs
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#
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# Device configuration
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#
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mainbus0 at root # Processor Local Bus
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cpunode* at mainbus? node ?
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gpio* at gpiobus?
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cpu* at cpunode?
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obio0 at cpunode? # On-chip Peripheral Bus
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#nandfcm* at obio0 cs ? # nand flash
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#nand* at nandfcm?
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#flash* at nand?
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# NOR Flash
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#options NOR_VERBOSE
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cfi0 at obio0 cs 0
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nor* at cfi?
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flash* at nor? offset 0 size 0x1000000
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e500wdog* at cpunode? # Watchdog timer
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ddrc* at cpunode?
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duart* at cpunode?
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com* at duart? port ?
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options CONSADDR="DUART1_BASE"
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tsec0 at cpunode? flags 0x002 # Enhanced 3-Speed Ethernet Controller
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tsec1 at cpunode? flags 0x103 # Enhanced 3-Speed Ethernet Controller
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ukphy* at mii?
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#options ETSEC_EVENT_COUNTERS
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diic* at cpunode? # i2c bus
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iic* at diic?
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#dsrtc* at iic1 addr 0x68 flags 1339 # RTC DS1339
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pq3pcie* at cpunode? # PCI-Express controller
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pci* at pq3pcie?
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ppb* at pci? dev ? function ? # PCI-PCI bridges
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pci* at ppb?
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ahcisata* at pci? dev ? function ?
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atabus* at ahcisata? channel ?
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wd* at atabus? drive ?
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ehci* at cpunode? # usb
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usb* at ehci?
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uhub* at usb?
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uhub* at uhub? port ?
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umass* at uhub? port ?
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scsibus* at umass? channel ?
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sd* at scsibus? target ? lun ?
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sdhc* at cpunode? # sdmmc
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sdmmc* at sdhc? # SD/MMC bus
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ld* at sdmmc?
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#siisata* at pci? dev ? function ?
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#atabus* at siisata? channel ?
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#jmide* at pci? dev ? function ? # JMicron PCI-e PATA/SATA controllers
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#ahcisata* at jmide?
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#atabus* at ahcisata? channel ?
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#viaide* at pci? dev ? function ?
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#atabus* at viaide? channel ?
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#wd* at atabus? drive ?
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#rtk* at pci? dev ? function ?
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#wm* at pci? dev ? function ? # Intel Ethernet
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#inphy* at mii? phy ? # Intel 82555 PHYs
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#iophy* at mii? phy ? # Intel 82553 PHYs
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#makphy* at mii? phy ? # Marvell PHYs
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#ukphy* at mii? phy ? # generic unknown PHYs
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pseudo-device loop # network loopback
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pseudo-device bpfilter # packet filter
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pseudo-device clockctl # user control of clock subsystem
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pseudo-device ksyms # /dev/ksyms
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pseudo-device pty # pseudo-terminals
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pseudo-device kttcp # kernel ttcp
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pseudo-device vlan # 802.1Q VLANs
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9
sys/arch/evbppc/conf/TWRP1025.MP
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9
sys/arch/evbppc/conf/TWRP1025.MP
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# $NetBSD: TWRP1025.MP,v 1.1 2012/07/15 08:44:56 matt Exp $
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#
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# TWRP1025 kernel, plus multiprocessor support.
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include "arch/evbppc/conf/TWRP1025"
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options MULTIPROCESSOR
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# this option may cause trouble under very high interrupt load
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#options OPENPIC_DISTRIBUTE # let all CPUs serve interrupts
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@ -1,9 +1,9 @@
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# $NetBSD: files.mpc85xx,v 1.8 2012/07/09 17:36:55 matt Exp $
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# $NetBSD: files.mpc85xx,v 1.9 2012/07/15 08:44:56 matt Exp $
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#
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# mpc85xx-specific configuration info
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defflag opt_mpc85xx.h MPC8536 MPC8544 MPC8548 MPC8555 MPC8568 MPC8572
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P2020 CADMUS PIXIS E500_WDOG_STACK
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P1025 P2020 CADMUS PIXIS E500_WDOG_STACK
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defparam opt_mpc85xx.h SYS_CLK MEMSIZE
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file arch/evbppc/mpc85xx/autoconf.c
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.24 2012/07/07 08:06:51 skrll Exp $ */
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/* $NetBSD: machdep.c,v 1.25 2012/07/15 08:44:56 matt Exp $ */
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/*-
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* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
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* All rights reserved.
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@ -205,12 +205,15 @@ static struct consdev e500_earlycons = {
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*/
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static const struct cpunode_locators mpc8548_cpunode_locs[] = {
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{ "cpu", 0, 0, 0, 0, { 0 }, 0, /* not a real device */
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{ 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } },
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#if defined(MPC8572) || defined(P2020)
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{ 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
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SVR_P1025v1 >> 16 } },
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#if defined(MPC8572) || defined(P2020) || defined(P1025)
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{ "cpu", 0, 0, 1, 0, { 0 }, 0, /* not a real device */
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{ SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } },
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{ SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
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SVR_P1025v1 >> 16 } },
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{ "cpu", 0, 0, 2, 0, { 0 }, 0, /* not a real device */
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{ SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } },
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{ SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
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SVR_P1025v1 >> 16 } },
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#endif
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{ "wdog" }, /* not a real device */
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{ "duart", DUART1_BASE, 2*DUART_SIZE, 0,
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@ -219,12 +222,14 @@ static const struct cpunode_locators mpc8548_cpunode_locs[] = {
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{ "tsec", ETSEC1_BASE, ETSEC_SIZE, 1,
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3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR },
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1 + ilog2(DEVDISR_TSEC1) },
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#if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) || defined(P2020)
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#if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) \
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|| defined(P2020) || defined(P1025)
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{ "tsec", ETSEC2_BASE, ETSEC_SIZE, 2,
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3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR },
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1 + ilog2(DEVDISR_TSEC2),
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{ SVR_MPC8548v1 >> 16, SVR_MPC8555v1 >> 16,
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SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } },
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SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
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SVR_P1025v1 >> 16 } },
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#endif
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#if defined(MPC8544) || defined(MPC8536)
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{ "tsec", ETSEC3_BASE, ETSEC_SIZE, 2,
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@ -232,12 +237,12 @@ static const struct cpunode_locators mpc8548_cpunode_locs[] = {
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1 + ilog2(DEVDISR_TSEC3),
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{ SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } },
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#endif
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#if defined(MPC8548) || defined(MPC8572) || defined(P2020)
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#if defined(MPC8548) || defined(MPC8572) || defined(P1025) || defined(P2020)
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{ "tsec", ETSEC3_BASE, ETSEC_SIZE, 3,
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3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR },
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1 + ilog2(DEVDISR_TSEC3),
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{ SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16,
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SVR_P2020v2 >> 16 } },
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SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 } },
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#endif
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#if defined(MPC8548) || defined(MPC8572)
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{ "tsec", ETSEC4_BASE, ETSEC_SIZE, 4,
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@ -308,25 +313,29 @@ static const struct cpunode_locators mpc8548_cpunode_locs[] = {
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1 + ilog2(DEVDISR_PCI2),
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{ SVR_MPC8548v1 >> 16 }, },
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#endif
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#if defined(MPC8572) || defined(P2020)
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#if defined(MPC8572) || defined(P1025) || defined(P2020)
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{ "pcie", PCIE1_BASE, PCI_SIZE, 1,
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1, { ISOURCE_PCIEX },
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1 + ilog2(DEVDISR_PCIE),
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{ SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } },
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{ SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
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SVR_P1025v1 >> 16 } },
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{ "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2,
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1, { ISOURCE_PCIEX2 },
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1 + ilog2(DEVDISR_PCIE2),
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{ SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } },
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{ SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
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SVR_P1025v1 >> 16 } },
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{ "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3,
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1, { ISOURCE_PCIEX3_MPC8572 },
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1 + ilog2(DEVDISR_PCIE3),
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{ SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } },
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{ SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
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SVR_P1025v1 >> 16 } },
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#endif
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#if defined(MPC8536) || defined(P2020)
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#if defined(MPC8536) || defined(P1025) || defined(P2020)
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{ "ehci", USB1_BASE, USB_SIZE, 1,
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1, { ISOURCE_USB1 },
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1 + ilog2(DEVDISR_USB1),
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{ SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16 } },
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{ SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16,
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SVR_P1025v1 >> 16 } },
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#endif
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#ifdef MPC8536
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{ "ehci", USB2_BASE, USB_SIZE, 2,
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@ -354,15 +363,15 @@ static const struct cpunode_locators mpc8548_cpunode_locs[] = {
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1 + ilog2(DEVDISR_ESDHC_12),
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{ SVR_MPC8536v1 >> 16 }, },
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#endif
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#if defined(P2020)
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#if defined(P1025) || defined(P2020)
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{ "spi", SPI_BASE, SPI_SIZE, 0,
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1, { ISOURCE_SPI },
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1 + ilog2(DEVDISR_SPI_28),
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{ SVR_P2020v2 >> 16 }, },
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{ SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 }, },
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{ "sdhc", ESDHC_BASE, ESDHC_SIZE, 0,
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1, { ISOURCE_ESDHC },
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1 + ilog2(DEVDISR_ESDHC_10),
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{ SVR_P2020v2 >> 16 }, },
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{ SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 }, },
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#endif
|
||||
//{ "sec", RNG_BASE, RNG_SIZE, 0, 0, },
|
||||
{ NULL }
|
||||
@ -611,6 +620,7 @@ getsvr(void)
|
||||
case SVR_MPC8543v1 >> 16: return SVR_MPC8548v1 >> 16;
|
||||
case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16;
|
||||
case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16;
|
||||
case SVR_P1016v1 >> 16: return SVR_P1025v1 >> 16;
|
||||
default: return svr;
|
||||
}
|
||||
}
|
||||
@ -634,6 +644,8 @@ socname(uint32_t svr)
|
||||
case SVR_MPC8572v1 >> 8: return "MPC8572";
|
||||
case SVR_P2020v2 >> 8: return "P2020";
|
||||
case SVR_P2010v2 >> 8: return "P2010";
|
||||
case SVR_P1016v1 >> 8: return "P1016";
|
||||
case SVR_P1025v1 >> 8: return "P1025";
|
||||
default:
|
||||
panic("%s: unknown SVR %#x", __func__, svr);
|
||||
}
|
||||
@ -1364,10 +1376,13 @@ cpu_startup(void)
|
||||
IST_LEVEL, 0, 1, 2, 3);
|
||||
break;
|
||||
#endif
|
||||
#if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) || defined(P2020)
|
||||
#if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) \
|
||||
|| defined(P1025) || defined(P2020)
|
||||
case SVR_MPC8536v1 >> 16:
|
||||
case SVR_MPC8544v1 >> 16:
|
||||
case SVR_MPC8572v1 >> 16:
|
||||
case SVR_P1016v1 >> 16:
|
||||
case SVR_P1025v1 >> 16:
|
||||
case SVR_P2010v2 >> 16:
|
||||
case SVR_P2020v2 >> 16:
|
||||
mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL,
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: pq3etsec.c,v 1.13 2012/05/07 23:04:22 matt Exp $ */
|
||||
/* $NetBSD: pq3etsec.c,v 1.14 2012/07/15 08:44:56 matt Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
@ -38,7 +38,7 @@
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
|
||||
__KERNEL_RCSID(0, "$NetBSD: pq3etsec.c,v 1.13 2012/05/07 23:04:22 matt Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: pq3etsec.c,v 1.14 2012/07/15 08:44:56 matt Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/cpu.h>
|
||||
@ -693,8 +693,6 @@ pq3etsec_ifinit(struct ifnet *ifp)
|
||||
struct pq3etsec_softc * const sc = ifp->if_softc;
|
||||
int error = 0;
|
||||
|
||||
KASSERT(!cpu_softintr_p());
|
||||
|
||||
sc->sc_maxfrm = max(ifp->if_mtu + 32, MCLBYTES);
|
||||
if (ifp->if_mtu > ETHERMTU_JUMBO)
|
||||
return error;
|
||||
@ -1134,7 +1132,7 @@ pq3etsec_mapcache_destroy(
|
||||
for (u_int i = 0; i < dmc->dmc_maxmaps; i++) {
|
||||
bus_dmamap_destroy(sc->sc_dmat, dmc->dmc_maps[i]);
|
||||
}
|
||||
kmem_free(dmc, dmc_size);
|
||||
kmem_intr_free(dmc, dmc_size);
|
||||
}
|
||||
|
||||
static int
|
||||
@ -1147,7 +1145,8 @@ pq3etsec_mapcache_create(
|
||||
{
|
||||
const size_t dmc_size =
|
||||
offsetof(struct pq3etsec_mapcache, dmc_maps[maxmaps]);
|
||||
struct pq3etsec_mapcache * const dmc = kmem_zalloc(dmc_size, KM_SLEEP);
|
||||
struct pq3etsec_mapcache * const dmc =
|
||||
kmem_intr_zalloc(dmc_size, KM_NOSLEEP);
|
||||
|
||||
dmc->dmc_maxmaps = maxmaps;
|
||||
dmc->dmc_nmaps = maxmaps;
|
||||
@ -1167,7 +1166,7 @@ pq3etsec_mapcache_create(
|
||||
bus_dmamap_destroy(sc->sc_dmat,
|
||||
dmc->dmc_maps[i]);
|
||||
}
|
||||
kmem_free(dmc, dmc_size);
|
||||
kmem_intr_free(dmc, dmc_size);
|
||||
return error;
|
||||
}
|
||||
KASSERT(dmc->dmc_maps[i] != NULL);
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: pq3gpio.c,v 1.7 2012/05/19 00:11:46 matt Exp $ */
|
||||
/* $NetBSD: pq3gpio.c,v 1.8 2012/07/15 08:44:56 matt Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
@ -41,7 +41,7 @@
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
|
||||
__KERNEL_RCSID(0, "$NetBSD: pq3gpio.c,v 1.7 2012/05/19 00:11:46 matt Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: pq3gpio.c,v 1.8 2012/07/15 08:44:56 matt Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/cpu.h>
|
||||
@ -109,6 +109,58 @@ pq3gpio_null_pin_ctl(void *v, int num, int ctl)
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(P1025)
|
||||
/*
|
||||
* P1025 has controllable input/output pins
|
||||
*/
|
||||
static void
|
||||
pq3gpio_pin_ctl(void *v, int num, int ctl)
|
||||
{
|
||||
struct pq3gpio_group * const gc = v;
|
||||
const size_t shift = gc->gc_pins[num].pin_num ^ 31;
|
||||
|
||||
uint64_t old_dir =
|
||||
((uint64_t)bus_space_read_4(gc->gc_bst, gc->gc_bsh, CPDIR1) << 32)
|
||||
| (bus_space_read_4(gc->gc_bst, gc->gc_bsh, CPDIR2) << 0);
|
||||
|
||||
uint32_t dir = 0;
|
||||
switch (ctl & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
|
||||
case GPIO_PIN_INPUT|GPIO_PIN_OUTPUT: dir = CPDIR_INOUT; break;
|
||||
case GPIO_PIN_OUTPUT: dir = CPDIR_OUT; break;
|
||||
case GPIO_PIN_INPUT: dir = CPDIR_INOUT; break;
|
||||
case 0: dir = CPDIR_DIS; break;
|
||||
}
|
||||
|
||||
uint64_t new_dir = (old_dir & (3ULL << (2 * shift)))
|
||||
| ((uint64_t)dir << (2 * shift));
|
||||
|
||||
if ((uint32_t)old_dir != (uint32_t)new_dir)
|
||||
bus_space_write_4(gc->gc_bst, gc->gc_bsh, CPDIR2,
|
||||
(uint32_t)new_dir);
|
||||
new_dir >>= 32;
|
||||
old_dir >>= 32;
|
||||
if ((uint32_t)old_dir != (uint32_t)new_dir)
|
||||
bus_space_write_4(gc->gc_bst, gc->gc_bsh, CPDIR1,
|
||||
(uint32_t)new_dir);
|
||||
|
||||
/*
|
||||
* Now handle opendrain
|
||||
*/
|
||||
uint32_t old_odr = bus_space_read_4(gc->gc_bst, gc->gc_bsh, CPODR);
|
||||
uint32_t new_odr = old_odr;
|
||||
uint32_t odr_mask = 1UL << shift;
|
||||
|
||||
if (ctl & GPIO_PIN_OPENDRAIN) {
|
||||
new_odr |= odr_mask;
|
||||
} else {
|
||||
new_odr &= ~odr_mask;
|
||||
}
|
||||
|
||||
if (old_odr != new_odr)
|
||||
bus_space_write_4(gc->gc_bst, gc->gc_bsh, CPODR, new_odr);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(MPC8536) || defined(P2020)
|
||||
/*
|
||||
* MPC8536 / P20x0 have controllable input/output pins
|
||||
@ -327,6 +379,55 @@ pq3gpio_mpc8548_attach(device_t self, bus_space_tag_t bst,
|
||||
}
|
||||
#endif /* MPC8548 */
|
||||
|
||||
#ifdef P1025
|
||||
static void
|
||||
pq3gpio_p1025_attach(device_t self, bus_space_tag_t bst,
|
||||
bus_space_handle_t bsh, u_int svr)
|
||||
{
|
||||
static const uint32_t gpio2pmuxcr_map[][4] = {
|
||||
{ 0, __BIT(12), 0, PMUXCR_SDHC_WP },
|
||||
{ __BIT(15), __BIT(8), 0, PMUXCR_USB1 },
|
||||
{ __BITS(14,4)|__BIT(16)|__BITS(27,17)|__BIT(30),
|
||||
__BIT(1)|__BITS(3,2), 0, PMUXCR_QE0 },
|
||||
{ __BITS(3,1), 0, 0, PMUXCR_QE3 },
|
||||
{ 0, __BITS(17,14), 0, PMUXCR_QE8 },
|
||||
{ __BIT(29), __BITS(19,18), 0, PMUXCR_QE9 },
|
||||
{ 0, __BITS(22,21), 0, PMUXCR_QE10 },
|
||||
{ 0, __BITS(28,23), 0, PMUXCR_QE11 },
|
||||
{ 0, __BIT(20), 0, PMUXCR_QE12 },
|
||||
};
|
||||
|
||||
uint32_t pinmask[3] = {
|
||||
0xffffffff, 0xffffffff, 0xffffffff
|
||||
}; /* assume all bits are valid */
|
||||
const uint32_t pmuxcr = cpu_read_4(GLOBAL_BASE + PMUXCR);
|
||||
for (size_t i = 0; i < __arraycount(gpio2pmuxcr_map); i++) {
|
||||
if (pmuxcr & gpio2pmuxcr_map[i][3]) {
|
||||
pinmask[0] &= ~gpio2pmuxcr_map[i][0];
|
||||
pinmask[1] &= ~gpio2pmuxcr_map[i][1];
|
||||
pinmask[2] &= ~gpio2pmuxcr_map[i][2];
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Create GPIO pin groups
|
||||
*/
|
||||
for (size_t i = 0; i < 3; i++) {
|
||||
if (pinmask[i]) {
|
||||
bus_space_handle_t bsh2;
|
||||
aprint_normal_dev(self,
|
||||
"gpio[%c]: %zu input/output/opendrain pins\n",
|
||||
"abc"[i], popcount32(pinmask[i]));
|
||||
bus_space_subregion(bst, bsh, CPBASE(i), 0x20, &bsh2);
|
||||
pq3gpio_group_create(self, bst, bsh2, CPDAT,
|
||||
pinmask[0],
|
||||
GPIO_PIN_INPUT|GPIO_PIN_OUTPUT|GPIO_PIN_OPENDRAIN,
|
||||
pq3gpio_pin_ctl);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* P1025 */
|
||||
|
||||
#ifdef P2020
|
||||
static void
|
||||
pq3gpio_p20x0_attach(device_t self, bus_space_tag_t bst,
|
||||
@ -386,6 +487,10 @@ static const struct pq3gpio_svr_info {
|
||||
{ SVR_MPC8536v1 >> 16, pq3gpio_mpc8536_attach,
|
||||
GPIO_BASE, GPIO_SIZE },
|
||||
#endif
|
||||
#ifdef P1025
|
||||
{ SVR_P1025v1 >> 16, pq3gpio_p1025_attach,
|
||||
GLOBAL_BASE, GLOBAL_SIZE },
|
||||
#endif
|
||||
#ifdef P2020
|
||||
{ SVR_P2020v2 >> 16, pq3gpio_p20x0_attach,
|
||||
GPIO_BASE, GPIO_SIZE },
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: e500_intr.c,v 1.18 2012/07/09 11:40:19 matt Exp $ */
|
||||
/* $NetBSD: e500_intr.c,v 1.19 2012/07/15 08:44:56 matt Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
@ -39,7 +39,7 @@
|
||||
#define __INTR_PRIVATE
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: e500_intr.c,v 1.18 2012/07/09 11:40:19 matt Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: e500_intr.c,v 1.19 2012/07/15 08:44:56 matt Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/proc.h>
|
||||
@ -319,6 +319,30 @@ const struct e500_intr_name mpc8572_onchip_intr_names[] = {
|
||||
|
||||
INTR_INFO_DECL(mpc8572, MPC8572);
|
||||
#endif
|
||||
|
||||
#ifdef P1025
|
||||
#define p1025_external_intr_names default_external_intr_names
|
||||
const struct e500_intr_name p1025_onchip_intr_names[] = {
|
||||
{ ISOURCE_PCIEX3_MPC8572, "pcie3" },
|
||||
{ ISOURCE_ETSEC1_G1_TX, "etsec1-g1-tx" },
|
||||
{ ISOURCE_ETSEC1_G1_RX, "etsec1-g1-rx" },
|
||||
{ ISOURCE_ETSEC1_G1_ERR, "etsec1-g1-error" },
|
||||
{ ISOURCE_ETSEC2_G1_TX, "etsec2-g1-tx" },
|
||||
{ ISOURCE_ETSEC2_G1_RX, "etsec2-g1-rx" },
|
||||
{ ISOURCE_ETSEC2_G1_ERR, "etsec2-g1-error" },
|
||||
{ ISOURCE_ETSEC3_G1_TX, "etsec3-g1-tx" },
|
||||
{ ISOURCE_ETSEC3_G1_RX, "etsec3-g1-rx" },
|
||||
{ ISOURCE_ETSEC3_G1_ERR, "etsec3-g1-error" },
|
||||
{ ISOURCE_DMA2_CHAN1, "dma2-chan1" },
|
||||
{ ISOURCE_DMA2_CHAN2, "dma2-chan2" },
|
||||
{ ISOURCE_DMA2_CHAN3, "dma2-chan3" },
|
||||
{ ISOURCE_DMA2_CHAN4, "dma2-chan4" },
|
||||
{ 0, "" },
|
||||
};
|
||||
|
||||
INTR_INFO_DECL(p1025, P1025);
|
||||
#endif
|
||||
|
||||
#ifdef P2020
|
||||
#define p20x0_external_intr_names default_external_intr_names
|
||||
const struct e500_intr_name p20x0_onchip_intr_names[] = {
|
||||
@ -1013,6 +1037,12 @@ e500_intr_init(void)
|
||||
*ii = mpc8572_intr_info;
|
||||
break;
|
||||
#endif
|
||||
#ifdef P1025
|
||||
case SVR_P1016v1 >> 16:
|
||||
case SVR_P1025v1 >> 16:
|
||||
*ii = p1025_intr_info;
|
||||
break;
|
||||
#endif
|
||||
#ifdef P2020
|
||||
case SVR_P2010v2 >> 16:
|
||||
case SVR_P2020v2 >> 16:
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: e500reg.h,v 1.10 2011/08/02 00:23:34 matt Exp $ */
|
||||
/* $NetBSD: e500reg.h,v 1.11 2012/07/15 08:44:56 matt Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
@ -458,9 +458,20 @@
|
||||
#define PMUXCR_USB1 __PPCBIT(5)
|
||||
#define PMUXCR_TSEC3_TS __PPCBIT(5)
|
||||
#define PMUXCR_USB2 __PPCBIT(6)
|
||||
#define PMUXCR_USB __PPCBIT(6)
|
||||
#define PMUXCR_USB_PCTL __PPCBITS(6,5)
|
||||
#define PMUXCR_USB __PPCBIT(6)
|
||||
#define PMUXCR_TSEC1 __PPCBIT(14)
|
||||
#define PMUXCR_DMA0 __PPCBIT(14)
|
||||
#define PMUXCR_DMA2 __PPCBIT(15)
|
||||
#define PMUXCR_QE0 __PPCBIT(16)
|
||||
#define PMUXCR_QE1 __PPCBIT(17)
|
||||
#define PMUXCR_QE2 __PPCBIT(18)
|
||||
#define PMUXCR_QE3 __PPCBIT(19)
|
||||
#define PMUXCR_QE8 __PPCBIT(24)
|
||||
#define PMUXCR_QE9 __PPCBIT(25)
|
||||
#define PMUXCR_QE10 __PPCBIT(26)
|
||||
#define PMUXCR_QE11 __PPCBIT(27)
|
||||
#define PMUXCR_QE12 __PPCBIT(28)
|
||||
#define PMUXCR_DMA1 __PPCBIT(30)
|
||||
#define PMUXCR_DMA3 __PPCBIT(31)
|
||||
|
||||
@ -518,6 +529,25 @@
|
||||
#define PVR 0x0A0 /* Processor version register */
|
||||
#define SVR 0x0A4 /* System version register */
|
||||
|
||||
/* Control Pin Registers (GPIO) for P1025 */
|
||||
#define CPBASE(n) (0x100+0x20*(n)) /* Control Pin (GPIO) base */
|
||||
#define CPODR 0x0000 /* Open Drain */
|
||||
#define CPDAT 0x0004 /* Output Data */
|
||||
#define CPDIR1 0x0008 /* Direction1 */
|
||||
#define CPDIR2 0x000c /* Direction2 */
|
||||
#define CPPAR1 0x0010 /* Pin Assignment1 */
|
||||
#define CPPAR2 0x0014 /* Pin Assignment2 */
|
||||
|
||||
#define CPDIR_DIS 0
|
||||
#define CPDIR_OUT 1
|
||||
#define CPDIR_IN 2
|
||||
#define CPDIR_INOUT 3
|
||||
|
||||
#define CPPAR_FUNC0 0
|
||||
#define CPPAR_FUNC1 1
|
||||
#define CPPAR_FUNC2 2
|
||||
#define CPPAR_FUNC3 3
|
||||
|
||||
/* Status Registers */
|
||||
#define RSTCR 0x0B0 /* Reset control register */
|
||||
#define HRESET_REQ __PPCBIT(30) /* hardware reset request */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: openpicreg.h,v 1.5 2011/08/02 00:22:02 matt Exp $ */
|
||||
/* $NetBSD: openpicreg.h,v 1.6 2012/07/15 08:44:57 matt Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
@ -275,6 +275,30 @@
|
||||
+ MPC8572_TIMERSOURCES \
|
||||
+ MPC8572_MISOURCES))
|
||||
|
||||
#define P1025_EXTERNALSOURCES 6
|
||||
#define P1025_ONCHIPSOURCES 64
|
||||
#define P1025_ONCHIPBITMAP { 0xbd1fffff, 0x01789c18 }
|
||||
#define P1025_IPISOURCES 4
|
||||
#define P1025_TIMERSOURCES 4
|
||||
#define P1025_MISOURCES 4
|
||||
#define P1025_MSIGROUPSOURCES 8
|
||||
#define P1025_NCPUS 2
|
||||
#define P1025_SOURCES /* 102 */ \
|
||||
(P1025_EXTERNALSOURCES \
|
||||
+ P1025_ONCHIPSOURCES \
|
||||
+ P1025_MSIGROUPSOURCES \
|
||||
+ P1025_NCPUS*(P1025_IPISOURCES \
|
||||
+ P1025_TIMERSOURCES \
|
||||
+ P1025_MISOURCES))
|
||||
#define P1016_NCPUS 1
|
||||
#define P1016_SOURCES \
|
||||
(P1025_EXTERNALSOURCES \
|
||||
+ P1025_ONCHIPSOURCES \
|
||||
+ P1025_MSIGROUPSOURCES \
|
||||
+ P1016_NCPUS*(P1025_IPISOURCES \
|
||||
+ P1025_TIMERSOURCES \
|
||||
+ P1025_MISOURCES))
|
||||
|
||||
#define P20x0_EXTERNALSOURCES 12
|
||||
#define P20x0_ONCHIPSOURCES 64
|
||||
#define P20x0_ONCHIPBITMAP { 0xbd1ff7ff, 0xf17005e7 }
|
||||
@ -311,31 +335,38 @@
|
||||
#define IRQ_SPURIOUS 0xffff
|
||||
|
||||
#define ISOURCE_L2 0
|
||||
#define ISOURCE_ERROR 0
|
||||
#define ISOURCE_ECM 1
|
||||
#define ISOURCE_ETSEC1_G1_TX 1 /* P1025 */
|
||||
#define ISOURCE_DDR 2
|
||||
#define ISOURCE_ETSEC1_G1_RX 2 /* P1025 */
|
||||
#define ISOURCE_LBC 3
|
||||
#define ISOURCE_DMA_CHAN1 4
|
||||
#define ISOURCE_DMA_CHAN2 5
|
||||
#define ISOURCE_DMA_CHAN3 6
|
||||
#define ISOURCE_DMA_CHAN4 7
|
||||
#define ISOURCE_PCIEX3_MPC8572 8 /* MPC8572/P20x0 */
|
||||
#define ISOURCE_PCIEX3_MPC8572 8 /* MPC8572/P20x0/P1025 */
|
||||
#define ISOURCE_PCI1 8 /* MPC8548/MPC8544/MPC8536/MPC8555 */
|
||||
#define ISOURCE_ETSEC1_G1_ERR 8 /* P1025 */
|
||||
#define ISOURCE_PCI2 9 /* MPC8548 */
|
||||
#define ISOURCE_PCIEX2 9 /* MPC8544/MPC8572/MPC8536/P20x0 */
|
||||
#define ISOURCE_ETSEC3_G1_TX 9 /* P1025 */
|
||||
#define ISOURCE_PCIEX 10
|
||||
#define ISOURCE_ETSEC3_G1_RX 10 /* P1025 */
|
||||
#define ISOURCE_PCIEX3 11 /* MPC8544/MPC8536 */
|
||||
#define ISOURCE_USB1 12 /* MPC8536/P20x0 */
|
||||
#define ISOURCE_ETSEC3_G1_ERR 11 /* P1025 */
|
||||
#define ISOURCE_USB1 12 /* MPC8536/P20x0/P1025 */
|
||||
#define ISOURCE_ETSEC1_TX 13
|
||||
#define ISOURCE_ETSEC1_RX 14
|
||||
#define ISOURCE_ETSEC3_TX 15
|
||||
#define ISOURCE_ETSEC3_RX 16
|
||||
#define ISOURCE_ETSEC3_ERR 17
|
||||
#define ISOURCE_ETSEC1_ERR 18
|
||||
#define ISOURCE_ETSEC2_TX 19 /* !MPC8544/!MPC8536 */
|
||||
#define ISOURCE_ETSEC2_RX 20 /* !MPC8544/!MPC8536 */
|
||||
#define ISOURCE_ETSEC4_TX 21 /* !MPC8544/!MPC8536/!P20x0 */
|
||||
#define ISOURCE_ETSEC4_RX 22 /* !MPC8544/!MPC8536/!P20x0 */
|
||||
#define ISOURCE_ETSEC4_ERR 23 /* !MPC8544/!MPC8536/!P20x0 */
|
||||
#define ISOURCE_ETSEC2_TX 19 /* !MPC8544/!MPC8536/!P1025 */
|
||||
#define ISOURCE_ETSEC2_RX 20 /* !MPC8544/!MPC8536/!P1025 */
|
||||
#define ISOURCE_ETSEC4_TX 21 /* !MPC8544/!MPC8536/!P20x0/!P1025 */
|
||||
#define ISOURCE_ETSEC4_RX 22 /* !MPC8544/!MPC8536/!P20x0/!P1025 */
|
||||
#define ISOURCE_ETSEC4_ERR 23 /* !MPC8544/!MPC8536/!P20x0/!P1025 */
|
||||
#define ISOURCE_ETSEC2_ERR 24 /* !MPC8544/!MPC8536 */
|
||||
#define ISOURCE_FEC 25 /* MPC8572 */
|
||||
#define ISOURCE_SATA2 25 /* MPC8536 */
|
||||
@ -347,34 +378,35 @@
|
||||
#define ISOURCE_QEB_LOW 30 /* MPC8568 */
|
||||
#define ISOURCE_USB2 30 /* MPC8536 */
|
||||
#define ISOURCE_GPIO 31 /* MPC8572/!MPC8548 */
|
||||
#define ISOURCE_QEB_PORT 31 /* MPC8568 */
|
||||
#define ISOURCE_SRIO_EWPU 32 /* !MPC8548&!P20x0 */
|
||||
#define ISOURCE_SRIO_ODBELL 33 /* !MPC8548&!P20x0 */
|
||||
#define ISOURCE_SRIO_IDBELL 34 /* !MPC8548&!P20x0 */
|
||||
#define ISOURCE_35 35
|
||||
#define ISOURCE_36 36
|
||||
#define ISOURCE_SRIO_OMU1 37 /* !MPC8548&!P20x0 */
|
||||
#define ISOURCE_SRIO_IMU1 38 /* !MPC8548&!P20x0 */
|
||||
#define ISOURCE_SRIO_OMU2 39 /* !MPC8548&!P20x0 */
|
||||
#define ISOURCE_SRIO_IMU2 40 /* !MPC8548&!P20x0 */
|
||||
#define ISOURCE_QEB_PORT 31 /* MPC8568/P1025 */
|
||||
#define ISOURCE_SRIO_EWPU 32 /* !MPC8548&!P20x0&!P1025 */
|
||||
#define ISOURCE_SRIO_ODBELL 33 /* !MPC8548&!P20x0&!P1025 */
|
||||
#define ISOURCE_SRIO_IDBELL 34 /* !MPC8548&!P20x0&!P1025 */
|
||||
#define ISOURCE_ETSEC2_G1_TX 35 /* P1025 */
|
||||
#define ISOURCE_ETSEC2_G1_RX 36 /* P1025 */
|
||||
#define ISOURCE_SRIO_OMU1 37 /* !MPC8548&!P20x0&!P1025 */
|
||||
#define ISOURCE_SRIO_IMU1 38 /* !MPC8548&!P20x0&!P1025 */
|
||||
#define ISOURCE_SRIO_OMU2 39 /* !MPC8548&!P20x0&!P1025 */
|
||||
#define ISOURCE_SRIO_IMU2 40 /* !MPC8548&!P20x0&!P1025 */
|
||||
#define ISOURCE_PME_GENERAL 41 /* MPC8572 */
|
||||
#define ISOURCE_SECURITY2 42 /* MPC8572|MPC8536|P20x0 */
|
||||
#define ISOURCE_SPI 43 /* MPC8536|P20x0 */
|
||||
#define ISOURCE_SECURITY2 42 /* MPC8572|MPC8536|P20x0|P1025 */
|
||||
#define ISOURCE_SPI 43 /* MPC8536|P20x0|P1025 */
|
||||
#define ISOURCE_QEB_IECC 43 /* MPC8568 */
|
||||
#define ISOURCE_USB3 44 /* MPC8536 */
|
||||
#define ISOURCE_QEB_MUECC 44 /* MPC8568 */
|
||||
#define ISOURCE_QEB_MUECC 44 /* MPC8568|P1025 */
|
||||
#define ISOURCE_TLU1 45 /* MPC8568/MPC8572 */
|
||||
#define ISOURCE_46 46
|
||||
#define ISOURCE_QEB_HIGH 47 /* MPC8548 */
|
||||
#define ISOURCE_QEB_HIGH 47 /* MPC8548|P1025 */
|
||||
#define ISOURCE_PME_CHAN1 48 /* MPC8572 */
|
||||
#define ISOURCE_PME_CHAN2 49 /* MPC8572 */
|
||||
#define ISOURCE_PME_CHAN3 50 /* MPC8572 */
|
||||
#define ISOURCE_PME_CHAN4 51 /* MPC8572 */
|
||||
#define ISOURCE_ETSEC1_PTP 52 /* MPC8572|MPC8536|P20x0 */
|
||||
#define ISOURCE_ETSEC2_PTP 53 /* MPC8572|P20x0 */
|
||||
#define ISOURCE_ETSEC3_PTP 54 /* MPC8572|MPC8536|P20x0 */
|
||||
#define ISOURCE_ETSEC2_G1_ERR 51 /* P1025 */
|
||||
#define ISOURCE_ETSEC1_PTP 52 /* MPC8572|MPC8536|P20x0|P1025 */
|
||||
#define ISOURCE_ETSEC2_PTP 53 /* MPC8572|P20x0|P1025 */
|
||||
#define ISOURCE_ETSEC3_PTP 54 /* MPC8572|MPC8536|P20x0|P1025 */
|
||||
#define ISOURCE_ETSEC4_PTP 55 /* MPC8572 */
|
||||
#define ISOURCE_ESDHC 56 /* MPC8536|P20x0 */
|
||||
#define ISOURCE_ESDHC 56 /* MPC8536|P20x0|P1025 */
|
||||
#define ISOURCE_57 57
|
||||
#define ISOURCE_SATA1 58 /* MPC8536 */
|
||||
#define ISOURCE_TLU2 59 /* MPC8572 */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: spr.h,v 1.8 2012/07/09 17:58:34 matt Exp $ */
|
||||
/* $NetBSD: spr.h,v 1.9 2012/07/15 08:44:57 matt Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
@ -68,9 +68,11 @@
|
||||
#define SVR_P1011v2 0x80e50020
|
||||
#define SVR_P1012v2 0x80e50120
|
||||
#define SVR_P1013v2 0x80e70020
|
||||
#define SVR_P1016v1 0x80e50310
|
||||
#define SVR_P1020v2 0x80e40020
|
||||
#define SVR_P1021v2 0x80e40120
|
||||
#define SVR_P1022v2 0x80e60020
|
||||
#define SVR_P1025v1 0x80e40310
|
||||
|
||||
#define SVR_SECURITY_P(svr) (((svr) & 0x00080000) != 0)
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user