255 lines
7.8 KiB
C
255 lines
7.8 KiB
C
/* $NetBSD: gt_mainbus.c,v 1.18 2013/04/21 15:42:11 kiyohara Exp $ */
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/*
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* Copyright (c) 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Allen Briggs for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: gt_mainbus.c,v 1.18 2013/04/21 15:42:11 kiyohara Exp $");
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#include "opt_ev64260.h"
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#include "opt_pci.h"
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#include "pci.h"
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/errno.h>
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#include <sys/extent.h>
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#define _POWERPC_BUS_DMA_PRIVATE
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#include <sys/bus.h>
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#include "opt_pci.h"
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pciconf.h>
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#include "opt_marvell.h"
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#include <dev/marvell/gtreg.h>
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#include <dev/marvell/gtvar.h>
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#include <dev/marvell/gtintrreg.h>
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#include <dev/marvell/gtpcireg.h>
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#include <dev/marvell/gtpcivar.h>
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#include <dev/marvell/marvellvar.h>
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#include <dev/marvell/gtsdmareg.h>
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#include <dev/marvell/gtmpscreg.h>
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#ifdef MPSC_CONSOLE
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#include <dev/marvell/gtmpscvar.h>
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#endif
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#include <evbppc/ev64260/ev64260.h>
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#include <powerpc/pic/picvar.h>
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static int gt_match(device_t, cfdata_t, void *);
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static void gt_attach(device_t, device_t, void *);
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void gtpci_md_conf_interrupt(void *, int, int, int, int, int *);
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int gtpci_md_conf_hook(void *, int, int, int, pcireg_t);
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CFATTACH_DECL_NEW(gt, sizeof(struct gt_softc), gt_match, gt_attach, NULL, NULL);
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struct gtpci_prot gtpci_prot = {
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GTPCI_GT64260_ACBL_PCISWAP_NOSWAP |
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GTPCI_GT64260_ACBL_WBURST_8_QW |
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GTPCI_GT64260_ACBL_RDMULPREFETCH |
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GTPCI_GT64260_ACBL_RDLINEPREFETCH |
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GTPCI_GT64260_ACBL_RDPREFETCH |
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GTPCI_GT64260_ACBL_PREFETCHEN,
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0,
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};
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int
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gt_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct mainbus_attach_args *mba = aux;
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if (strcmp(mba->mba_name, "gt") != 0)
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return 0;
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return 1;
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}
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void
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gt_attach(device_t parent, device_t self, void *aux)
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{
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extern struct powerpc_bus_space ev64260_gt_bs_tag;
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extern struct powerpc_bus_dma_tag ev64260_bus_dma_tag;
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struct mainbus_attach_args *mba = aux;
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struct gt_softc *sc = device_private(self);
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uint32_t cpumstr, cr, r;
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sc->sc_dev = self;
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sc->sc_addr = mba->mba_addr;
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sc->sc_iot = &ev64260_gt_bs_tag;
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sc->sc_dmat = &ev64260_bus_dma_tag;
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#ifdef MPSC_CONSOLE
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{
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/* First, unmap already mapped console space. */
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gtmpsc_softc_t *gtmpsc = >mpsc_cn_softc;
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bus_space_unmap(gtmpsc->sc_iot, gtmpsc->sc_mpsch, GTMPSC_SIZE);
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bus_space_unmap(gtmpsc->sc_iot, gtmpsc->sc_sdmah, GTSDMA_SIZE);
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}
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#endif
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if (bus_space_map(sc->sc_iot, sc->sc_addr, GT_SIZE, 0, &sc->sc_ioh) !=
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0) {
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aprint_error_dev(self, "registers map failed\n");
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return;
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}
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#ifdef MPSC_CONSOLE
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{
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/* Next, remap console space. */
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gtmpsc_softc_t *gtmpsc = >mpsc_cn_softc;
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if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
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GTMPSC_BASE(gtmpsc->sc_unit), GTMPSC_SIZE,
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>mpsc->sc_mpsch)) {
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aprint_error_dev(self, "Cannot map MPSC registers\n");
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return;
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}
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if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
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GTSDMA_BASE(gtmpsc->sc_unit), GTSDMA_SIZE,
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>mpsc->sc_sdmah)) {
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aprint_error_dev(self, "Cannot map SDMA registers\n");
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return;
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}
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}
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#endif
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/*
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* Set MPSC Routing:
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* MR0 --> Serial Port 0
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* MR1 --> Serial Port 1
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*/
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTMPSC_MRR, GTMPSC_MRR_RES);
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/*
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* RX and TX Clock Routing:
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* CRR0 --> BRG0
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* CRR1 --> BRG1
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*/
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cr = GTMPSC_CRR(0, GTMPSC_CRR_BRG0) | GTMPSC_CRR(1, GTMPSC_CRR_BRG1);
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTMPSC_RCRR, cr);
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTMPSC_TCRR, cr);
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/*
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* Setup Multi-Purpose Pins (MPP).
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* Change to GPP.
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* GPP 21 (DUART channel A intr)
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* GPP 22 (DUART channel B intr)
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* GPP 26 (RTC INT)
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* GPP 27 (PCI 0 INTA)
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* GPP 29 (PCI 1 INTA)
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*/
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#define PIN2SHIFT(pin) ((pin % 8) * 4)
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r = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_MPP_Control2);
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r |= ((0xf << PIN2SHIFT(21)) | (0xf << PIN2SHIFT(22)));
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_MPP_Control2, r);
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r = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_MPP_Control3);
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r |= ((0xf << PIN2SHIFT(26)));
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r |= ((0xf << PIN2SHIFT(27)) | (0xf << PIN2SHIFT(29)));
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_MPP_Control3, r);
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/* Also configure GPP. */
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#define GPP_EXTERNAL_INTERRUPS \
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((1 << 21) | (1 << 22) | (1 << 26) | (1 << 27) | (1 << 29))
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r = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_GPP_IO_Control);
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r &= ~GPP_EXTERNAL_INTERRUPS;
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_IO_Control, r);
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r = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Level_Control);
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r |= GPP_EXTERNAL_INTERRUPS;
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Level_Control, r);
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/* clear interrupts */
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, ICR_CIM_LO, 0);
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, ICR_CIM_HI, 0);
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Cause,
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~GPP_EXTERNAL_INTERRUPS);
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Mask,
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GPP_EXTERNAL_INTERRUPS);
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discovery_pic->pic_cookie = sc;
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intr_establish(IRQ_GPP7_0, IST_LEVEL, IPL_HIGH,
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pic_handle_intr, discovery_gpp_pic[0]);
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intr_establish(IRQ_GPP15_8, IST_LEVEL, IPL_HIGH,
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pic_handle_intr, discovery_gpp_pic[1]);
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intr_establish(IRQ_GPP23_16, IST_LEVEL, IPL_HIGH,
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pic_handle_intr, discovery_gpp_pic[2]);
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intr_establish(IRQ_GPP31_24, IST_LEVEL, IPL_HIGH,
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pic_handle_intr, discovery_gpp_pic[3]);
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cpumstr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_CPU_Master_Ctl);
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cpumstr &= ~(GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock);
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_CPU_Master_Ctl, cpumstr);
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gt_attach_common(sc);
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}
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void
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gtpci_md_conf_interrupt(void *v, int bus, int dev, int pin, int swiz,
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int *iline)
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{
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#ifdef PCI_NETBSD_CONFIGURE
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struct gtpci_softc *sc = v;
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*iline = (sc->sc_unit == 0 ? 27 : 29);
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#define IRQ_GPP_BASE (discovery_pic->pic_numintrs);
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if (*iline != 0xff)
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*iline += IRQ_GPP_BASE;
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#endif /* PCI_NETBSD_CONFIGURE */
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}
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int
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gtpci_md_conf_hook(void *v, int bus, int dev, int func, pcireg_t id)
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{
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struct gtpci_softc *sc = v;
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return gtpci_conf_hook(sc->sc_pc, bus, dev, func, id);
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}
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void *
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marvell_intr_establish(int irq, int ipl, int (*func)(void *), void *arg)
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{
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/* pass through */
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return intr_establish(irq, IST_LEVEL, ipl, func, arg);
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}
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