31513e4110
http://www.simtec.co.uk/products/EB7500ATX/ also available with RISC-OS as a RiscStation: http://www.riscstation.co.uk/html/products.html This is basic bootstrap with support for ide and networking, currently only tested with booting from ABLE, and not RISC-OS. I would have placed it into evbarm, but iomd doesn't appear to use the same interrupt files as evbarm. I'll check it into here for now, until iomd uses the common interrupt code.
194 lines
4.7 KiB
C
194 lines
4.7 KiB
C
/* $NetBSD: rsbus_io.c,v 1.1 2004/01/03 14:31:28 chris Exp $ */
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/*
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* Copyright (c) 1997 Mark Brinicombe.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* bus_space I/O functions for rsbus
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rsbus_io.c,v 1.1 2004/01/03 14:31:28 chris Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <machine/bus.h>
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/* Proto types for all the bus_space structure functions */
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bs_protos(rsbus);
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bs_protos(bs_notimpl);
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bs_protos(mainbus);
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/* Declare the rsbus bus space tag */
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struct bus_space rsbus_bs_tag = {
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/* cookie */
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(void *) 2, /* Shift to apply to registers */
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/* mapping/unmapping */
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mainbus_bs_map,
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mainbus_bs_unmap,
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mainbus_bs_subregion,
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/* allocation/deallocation */
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mainbus_bs_alloc,
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mainbus_bs_free,
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/* get kernel virtual address */
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0, /* there is no linear mapping */
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/* mmap bus space for userland */
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mainbus_bs_mmap,
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/* barrier */
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mainbus_bs_barrier,
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/* read (single) */
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rsbus_bs_r_1,
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rsbus_bs_r_2,
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rsbus_bs_r_4,
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bs_notimpl_bs_r_8,
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/* read multiple */
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rsbus_bs_rm_1,
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rsbus_bs_rm_2,
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bs_notimpl_bs_rm_4,
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bs_notimpl_bs_rm_8,
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/* read region */
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rsbus_bs_rr_1,
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rsbus_bs_rr_2,
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bs_notimpl_bs_rr_4,
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bs_notimpl_bs_rr_8,
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/* write (single) */
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rsbus_bs_w_1,
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rsbus_bs_w_2,
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rsbus_bs_w_4,
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bs_notimpl_bs_w_8,
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/* write multiple */
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rsbus_bs_wm_1,
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rsbus_bs_wm_2,
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bs_notimpl_bs_wm_4,
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bs_notimpl_bs_wm_8,
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/* write region */
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rsbus_bs_wr_1,
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rsbus_bs_wr_2,
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bs_notimpl_bs_wr_4,
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bs_notimpl_bs_wr_8,
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/* set multiple */
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bs_notimpl_bs_sm_1,
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bs_notimpl_bs_sm_2,
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bs_notimpl_bs_sm_4,
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bs_notimpl_bs_sm_8,
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/* set region */
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rsbus_bs_sr_1,
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rsbus_bs_sr_2,
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bs_notimpl_bs_sr_4,
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bs_notimpl_bs_sr_8,
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/* copy */
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bs_notimpl_bs_c_1,
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bs_notimpl_bs_c_2,
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bs_notimpl_bs_c_4,
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bs_notimpl_bs_c_8,
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};
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/* bus space functions */
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/* Rough-and-ready implementations from arm26 */
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void
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rsbus_bs_rr_1(void *cookie, bus_space_handle_t bsh,
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bus_size_t offset, u_int8_t *datap, bus_size_t count)
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{
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int i;
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for (i = 0; i < count; i++)
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datap[i] = rsbus_bs_r_1(cookie, bsh, offset + i);
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}
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void
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rsbus_bs_rr_2(void *cookie, bus_space_handle_t bsh,
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bus_size_t offset, u_int16_t *datap, bus_size_t count)
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{
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int i;
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for (i = 0; i < count; i++)
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datap[i] = rsbus_bs_r_2(cookie, bsh, offset + i);
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}
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void
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rsbus_bs_wr_1(void *cookie, bus_space_handle_t bsh,
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bus_size_t offset, u_int8_t const *datap,
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bus_size_t count)
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{
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int i;
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for (i = 0; i < count; i++)
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rsbus_bs_w_1(cookie, bsh, offset + i, datap[i]);
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}
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void
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rsbus_bs_wr_2(void *cookie, bus_space_handle_t bsh,
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bus_size_t offset, u_int16_t const *datap,
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bus_size_t count)
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{
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int i;
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for (i = 0; i < count; i++)
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rsbus_bs_w_2(cookie, bsh, offset + i, datap[i]);
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}
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void
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rsbus_bs_sr_1(void *cookie, bus_space_handle_t bsh,
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bus_size_t offset, u_int8_t value, bus_size_t count)
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{
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int i;
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for (i = 0; i < count; i++)
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rsbus_bs_w_1(cookie, bsh, offset + i, value);
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}
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void
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rsbus_bs_sr_2(void *cookie, bus_space_handle_t bsh,
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bus_size_t offset, u_int16_t value, bus_size_t count)
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{
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int i;
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for (i = 0; i < count; i++)
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rsbus_bs_w_2(cookie, bsh, offset + i, value);
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}
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