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First part of support for the eb7500atx board from simtec:

Browse Source 
http://www.simtec.co.uk/products/EB7500ATX/

also available with RISC-OS as a RiscStation:
http://www.riscstation.co.uk/html/products.html

This is basic bootstrap with support for ide and networking, currently only
tested with booting from ABLE, and not RISC-OS.

I would have placed it into evbarm, but iomd doesn't appear to use the same
interrupt files as evbarm.  I'll check it into here for now, until iomd
uses the common interrupt code.
This commit is contained in:
chris 2004-01-03 14:31:28 +00:00
parent 9bdabb5f9b
commit 31513e4110
8 changed files with 2187 additions and 0 deletions
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1035
sys/arch/acorn32/eb7500atx/eb7500atx_machdep.c Normal file
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sys/arch/acorn32/eb7500atx/if_cs.c Normal file
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/* $NetBSD: if_cs.c,v 1.1 2004/01/03 14:31:28 chris Exp $ */
/*
* Copyright 1997
* Digital Equipment Corporation. All rights reserved.
*
* This software is furnished under license and may be used and
* copied only in accordance with the following terms and conditions.
* Subject to these conditions, you may download, copy, install,
* use, modify and distribute this software in source and/or binary
* form. No title or ownership is transferred hereby.
*
* 1) Any source code used, modified or distributed must reproduce
* and retain this copyright notice and list of conditions as
* they appear in the source file.
*
* 2) No right is granted to use any trade name, trademark, or logo of
* Digital Equipment Corporation. Neither the "Digital Equipment
* Corporation" name nor any trademark or logo of Digital Equipment
* Corporation may be used to endorse or promote products derived
* from this software without the prior written permission of
* Digital Equipment Corporation.
*
* 3) This software is provided "AS-IS" and any express or implied
* warranties, including but not limited to, any implied warranties
* of merchantability, fitness for a particular purpose, or
* non-infringement are disclaimed. In no event shall DIGITAL be
* liable for any damages whatsoever, and in particular, DIGITAL
* shall not be liable for special, indirect, consequential, or
* incidental damages or damages for lost profits, loss of
* revenue or loss of use, whether such damages arise in contract,
* negligence, tort, under statute, in equity, at law or otherwise,
* even if advised of the possibility of such damage.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: if_cs.c,v 1.1 2004/01/03 14:31:28 chris Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/socket.h>
#include <sys/device.h>
#include "rnd.h"
#if NRND > 0
#include <sys/rnd.h>
#endif
#include <net/if.h>
#include <net/if_ether.h>
#include <net/if_media.h>
#include <machine/bus.h>
#include <machine/intr.h>
#include <sys/queue.h>
#include <uvm/uvm.h>
#include <machine/pmap.h>
#include <acorn32/eb7500atx/rsbus.h>
#include <dev/ic/cs89x0reg.h>
#include <dev/ic/cs89x0var.h>
/*
* the CS network interface is accessed at the following address locations:
* 030104f1 CS8920 PNP Low
* 03010600 03010640 CS8920 Default I/O registers
* 030114f1 CS8920 PNP High
* 03014000 03016000 CS8920 Default Memory
*
* IRQ is mapped as:
* CS8920 IRQ 3 INT5
*
* It must be configured as the following:
* The CS8920 PNP address should be configured for ISA base at 0x300
* to achieve the default register mapping as specified.
* Note memory addresses are all have bit 23 tied high in hardware.
* This only effects the value programmed into the CS8920 memory offset
* registers.
*
* Just to add to the fun the I/O registers are layed out as:
* xxxxR1R0
* xxxxR3R2
* xxxxR5R4
*
* This makes access to single registers hard (which does happen on a reset,
* as we've got to toggle the chip into 16bit mode)
*
* Network DRQ is connected to DRQ5
*/
/*
* make a private tag so that we can use mainbus's map/unmap
*/
static struct bus_space cs_rsbus_bs_tag;
int cs_pioc_probe __P((struct device *, struct cfdata *, void *));
void cs_pioc_attach __P((struct device *, struct device *, void *));
static u_int8_t cs_rbus_read_1(struct cs_softc *, bus_size_t);
CFATTACH_DECL(cs_rsbus, sizeof(struct cs_softc),
cs_pioc_probe, cs_pioc_attach, NULL, NULL);
/* Available media */
int cs_rbus_media [] = {
IFM_ETHER|IFM_10_T,
IFM_ETHER|IFM_10_T|IFM_FDX
};
int
cs_pioc_probe(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
/* for now it'll always attach */
return 1;
}
#if 0
struct isa_attach_args *ia = aux;
bus_space_tag_t iot = ia->ia_iot;
bus_space_tag_t memt = ia->ia_memt;
bus_space_handle_t ioh, memh;
struct cs_softc sc;
int rv = 0, have_io = 0, have_mem = 0;
u_int16_t isa_cfg, isa_membase;
int maddr, irq;
if (ia->ia_nio < 1)
return (0);
if (ia->ia_nirq < 1)
return (0);
if (ISA_DIRECT_CONFIG(ia))
return (0);
/*
* Disallow wildcarded I/O base.
*/
if (ia->ia_io[0].ir_addr == ISACF_PORT_DEFAULT)
return (0);
if (ia->ia_niomem > 0)
maddr = ia->ia_iomem[0].ir_addr;
else
maddr = ISACF_IOMEM_DEFAULT;
/*
* Map the I/O space.
*/
if (bus_space_map(ia->ia_iot, ia->ia_io[0].ir_addr, CS8900_IOSIZE,
0, &ioh))
goto out;
have_io = 1;
memset(&sc, 0, sizeof sc);
sc.sc_iot = iot;
sc.sc_ioh = ioh;
/* Verify that it's a Crystal product. */
if (CS_READ_PACKET_PAGE_IO(&sc, PKTPG_EISA_NUM) !=
EISA_NUM_CRYSTAL)
goto out;
/*
* Verify that it's a supported chip.
*/
switch (CS_READ_PACKET_PAGE_IO(&sc, PKTPG_PRODUCT_ID) &
PROD_ID_MASK) {
case PROD_ID_CS8900:
#ifdef notyet
case PROD_ID_CS8920:
case PROD_ID_CS8920M:
#endif
rv = 1;
}
/*
* If the IRQ or memory address were not specified, read the
* ISA_CFG EEPROM location.
*/
if (maddr == ISACF_IOMEM_DEFAULT ||
ia->ia_irq[0].ir_irq == ISACF_IRQ_DEFAULT) {
if (cs_verify_eeprom(&sc) == CS_ERROR) {
printf("cs_isa_probe: EEPROM bad or missing\n");
goto out;
}
if (cs_read_eeprom(&sc, EEPROM_ISA_CFG, &isa_cfg)
== CS_ERROR) {
printf("cs_isa_probe: unable to read ISA_CFG\n");
goto out;
}
}
/*
* If the IRQ wasn't specified, get it from the EEPROM.
*/
if (ia->ia_irq[0].ir_irq == ISACF_IRQ_DEFAULT) {
irq = isa_cfg & ISA_CFG_IRQ_MASK;
if (irq == 3)
irq = 5;
else
irq += 10;
} else
irq = ia->ia_irq[0].ir_irq;
/*
* If the memory address wasn't specified, get it from the EEPROM.
*/
if (maddr == ISACF_IOMEM_DEFAULT) {
if ((isa_cfg & ISA_CFG_MEM_MODE) == 0) {
/* EEPROM says don't use memory mode. */
goto out;
}
if (cs_read_eeprom(&sc, EEPROM_MEM_BASE, &isa_membase)
== CS_ERROR) {
printf("cs_isa_probe: unable to read MEM_BASE\n");
goto out;
}
isa_membase &= MEM_BASE_MASK;
maddr = (int)isa_membase << 8;
}
/*
* We now have a valid mem address; attempt to map it.
*/
if (bus_space_map(ia->ia_memt, maddr, CS8900_MEMSIZE, 0, &memh)) {
/* Can't map it; fall back on i/o-only mode. */
printf("cs_isa_probe: unable to map memory space\n");
maddr = ISACF_IOMEM_DEFAULT;
} else
have_mem = 1;
out:
if (have_io)
bus_space_unmap(iot, ioh, CS8900_IOSIZE);
if (have_mem)
bus_space_unmap(memt, memh, CS8900_MEMSIZE);
if (rv) {
ia->ia_nio = 1;
ia->ia_io[0].ir_size = CS8900_IOSIZE;
if (maddr == ISACF_IOMEM_DEFAULT)
ia->ia_niomem = 0;
else {
ia->ia_niomem = 1;
ia->ia_iomem[0].ir_addr = maddr;
ia->ia_iomem[0].ir_size = CS8900_MEMSIZE;
}
ia->ia_nirq = 1;
ia->ia_irq[0].ir_irq = irq;
}
return (rv);
}
#endif
void
cs_pioc_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct cs_softc *sc = (struct cs_softc *)self;
struct rsbus_attach_args *rs = (void *)aux;
u_int iobase;
/* member copy */
cs_rsbus_bs_tag = *rs->sa_iot;
/* registers are 4 byte aligned */
cs_rsbus_bs_tag.bs_cookie = (void *) 1;
sc->sc_iot = sc->sc_memt = &cs_rsbus_bs_tag;
/*
* Do DMA later
if (ia->ia_ndrq > 0)
isc->sc_drq = ia->ia_drq[0].ir_drq;
else
isc->sc_drq = -1;
*/
/* device always interrupts on 3 but that routes to IRQ 5 */
sc->sc_irq = 3;
printf("\n");
/*
* Map the device.
*/
iobase = 0x03010600;
printf("mapping iobase=0x%08x, for 0x%08x\n", iobase, CS8900_IOSIZE * 4);
if (bus_space_map(sc->sc_iot, iobase, CS8900_IOSIZE * 4,
0, &sc->sc_ioh)) {
printf("%s: unable to map i/o space\n", sc->sc_dev.dv_xname);
return;
}
#if 0
bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, PORT_PKTPG_PTR, PKTPG_EISA_NUM);
productID = bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, PORT_PKTPG_DATA);
printf("Result ID = 0x%08x\n", productID);
printf("cookie = %p\n", sc->sc_iot->bs_cookie);
{
volatile uint32_t *ptr = (void*) ((char *)((sc)->sc_ioh) + (PORT_PKTPG_PTR << 1));
volatile uint32_t *data =(void *)((char *)((sc)->sc_ioh) + (PORT_PKTPG_DATA << 1));
volatile char *pnplow = (char *)trunc_page((sc)->sc_ioh) + 0x4f1;
bus_space_handle_t tag2;
pt_entry_t *pte;
printf("ioh = %p, ptr = %p, data = %p\n", (void*)(sc)->sc_ioh, ptr, data);
*ptr = PKTPG_EISA_NUM;
productID = *data;
printf("Result ID2 = 0x%08x\n", productID);
pte = vtopte(trunc_page((sc)->sc_ioh));
printf("pte = %p, *pte = 0x%08x\n", pte, *pte);
printf("pnplow = %p, *pnplow = 0x%02x\n", pnplow, *pnplow);
if (bus_space_map(sc->sc_iot, 0x03011000, 0x1000,
0, &tag2)) {
printf("%s: unable to map i/o space\n", sc->sc_dev.dv_xname);
return;
}
pnplow = (char *)trunc_page(tag2) + 0x4f1;
printf("pnplow = %p, *pnplow = 0x%02x\n", pnplow, *pnplow);
*pnplow = 0x3;
*ptr = PKTPG_EISA_NUM;
productID = *data;
printf("Result ID2 = 0x%08x\n", productID);
}
#endif
#if 0
/*
* Map the memory space if it was specified. If we can do this,
* we set ourselves up to use memory mode forever. Otherwise,
* we fall back on I/O mode.
*/
if (ia->ia_iomem[0].ir_addr != ISACF_IOMEM_DEFAULT &&
ia->ia_iomem[0].ir_size == CS8900_MEMSIZE &&
CS8900_MEMBASE_ISVALID(ia->ia_iomem[0].ir_addr)) {
#endif
#if 0
printf("mapping iobase=0x%08x, for 0x%08x\n", iobase + 0x3A00,
CS8900_MEMSIZE * 4);
if (bus_space_map(sc->sc_memt, iobase + 0x3A00,
CS8900_MEMSIZE * 4, 0, &sc->sc_memh)) {
printf("%s: unable to map memory space\n",
sc->sc_dev.dv_xname);
} else {
sc->sc_cfgflags |= CFGFLG_MEM_MODE;
sc->sc_pktpgaddr = iobase + 0x3A00;
}
#endif
printf("Claiming IRQ\n");
sc->sc_ih = intr_claim(0x0B, IPL_NET, "cs", cs_intr, sc);
if (sc->sc_ih == NULL) {
printf("%s: unable to establish interrupt\n",
sc->sc_dev.dv_xname);
return;
}
/* DMA is for later */
sc->sc_dma_chipinit = NULL;
sc->sc_dma_attach = NULL;
sc->sc_dma_process_rx = NULL;
printf("Cs attach addr: 0x%04x\n", CS_READ_PACKET_PAGE(sc, PKTPG_IND_ADDR));
/* don't talk to the EEPROM, it seems that the cs driver doesn't use a
* normal layout */
sc->sc_cfgflags |= CFGFLG_NOT_EEPROM;
sc->sc_io_read_1 = cs_rbus_read_1;
cs_attach(sc, NULL, cs_rbus_media, sizeof(cs_rbus_media) / sizeof(cs_rbus_media[0]),
IFM_ETHER|IFM_10_T|IFM_FDX);
}
static u_int8_t
cs_rbus_read_1(struct cs_softc *sc, bus_size_t a)
{
bus_size_t offset;
/* this is rather warped if it's an even address then just use the
* bus_space_read_1
*/
if ((a & 1) == 0)
{
return bus_space_read_1(sc->sc_iot, sc->sc_ioh, a);
}
/* otherwise we've get to work out the aligned address and then add
* one */
/* first work out the offset */
offset = (a & ~1) << 1;
/* add the one */
offset++;
/* and read it, with no shift */
return sc->sc_iot->bs_r_1(0, (sc)->sc_ioh, offset);
}

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sys/arch/acorn32/eb7500atx/rsbus.c Normal file
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/* $NetBSD: rsbus.c,v 1.1 2004/01/03 14:31:28 chris Exp $ */
/*
* Copyright (c) 2002
* Ichiro FUKUHARA <ichiro@ichiro.org>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Ichiro FUKUHARA.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/param.h>
__KERNEL_RCSID(0, "$NetBSD: rsbus.c,v 1.1 2004/01/03 14:31:28 chris Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <machine/bus.h>
#include <acorn32/eb7500atx/rsbus.h>
#include "locators.h"
extern struct bus_space rsbus_bs_tag;
/* Declare prototypes */
static int rsbus_match(struct device *, struct cfdata *, void *);
static void rsbus_attach(struct device *, struct device *, void *);
static int rsbus_print(void *, const char *);
static int rsbus_search(struct device *, struct cfdata *, void *);
CFATTACH_DECL(rsbus, sizeof(struct rsbus_softc),
rsbus_match, rsbus_attach, NULL, NULL);
static int
rsbus_match(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
return(1);
}
static void
rsbus_attach(struct device *parent, struct device *self, void *aux)
{
struct rsbus_softc *sc = (void *) self;
sc->sc_iot = &rsbus_bs_tag;
printf("\n");
/*
* Attach each devices
*/
config_search(rsbus_search, self, NULL);
}
static int
rsbus_search(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct rsbus_softc *sc = (struct rsbus_softc *)parent;
struct rsbus_attach_args sa;
sa.sa_iot = sc->sc_iot;
sa.sa_addr = cf->cf_loc[RSBUSCF_ADDR];
sa.sa_size = cf->cf_loc[RSBUSCF_SIZE];
sa.sa_intr = cf->cf_loc[RSBUSCF_IRQ];
if (config_match(parent, cf, &sa) > 0)
config_attach(parent, cf, &sa, rsbus_print);
return (0);
}
static int
rsbus_print(aux, name)
void *aux;
const char *name;
{
struct rsbus_attach_args *sa = (struct rsbus_attach_args*)aux;
if (sa->sa_size)
aprint_normal(" addr 0x%lx", sa->sa_addr);
if (sa->sa_size > 1)
aprint_normal("-0x%lx", sa->sa_addr + sa->sa_size - 1);
if (sa->sa_intr > 1)
aprint_normal(" irq %d", sa->sa_intr);
return (UNCONF);
}

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/* $NetBSD: rsbus.h,v 1.1 2004/01/03 14:31:28 chris Exp $ */
#ifndef _RSBUS_H_
#define _RSBUS_H_
#include <sys/conf.h>
#include <sys/device.h>
#include <sys/queue.h>
#include <machine/bus.h>
struct rsbus_softc {
struct device sc_dev;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
};
struct rsbus_attach_args {
bus_space_tag_t sa_iot; /* Bus tag */
bus_addr_t sa_addr; /* i/o address */
bus_size_t sa_size;
int sa_intr;
};
#endif /* _RSBUS_H_ */

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/* $NetBSD: rsbus_io.c,v 1.1 2004/01/03 14:31:28 chris Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* bus_space I/O functions for rsbus
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: rsbus_io.c,v 1.1 2004/01/03 14:31:28 chris Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <machine/bus.h>
/* Proto types for all the bus_space structure functions */
bs_protos(rsbus);
bs_protos(bs_notimpl);
bs_protos(mainbus);
/* Declare the rsbus bus space tag */
struct bus_space rsbus_bs_tag = {
/* cookie */
(void *) 2, /* Shift to apply to registers */
/* mapping/unmapping */
mainbus_bs_map,
mainbus_bs_unmap,
mainbus_bs_subregion,
/* allocation/deallocation */
mainbus_bs_alloc,
mainbus_bs_free,
/* get kernel virtual address */
0, /* there is no linear mapping */
/* mmap bus space for userland */
mainbus_bs_mmap,
/* barrier */
mainbus_bs_barrier,
/* read (single) */
rsbus_bs_r_1,
rsbus_bs_r_2,
rsbus_bs_r_4,
bs_notimpl_bs_r_8,
/* read multiple */
rsbus_bs_rm_1,
rsbus_bs_rm_2,
bs_notimpl_bs_rm_4,
bs_notimpl_bs_rm_8,
/* read region */
rsbus_bs_rr_1,
rsbus_bs_rr_2,
bs_notimpl_bs_rr_4,
bs_notimpl_bs_rr_8,
/* write (single) */
rsbus_bs_w_1,
rsbus_bs_w_2,
rsbus_bs_w_4,
bs_notimpl_bs_w_8,
/* write multiple */
rsbus_bs_wm_1,
rsbus_bs_wm_2,
bs_notimpl_bs_wm_4,
bs_notimpl_bs_wm_8,
/* write region */
rsbus_bs_wr_1,
rsbus_bs_wr_2,
bs_notimpl_bs_wr_4,
bs_notimpl_bs_wr_8,
/* set multiple */
bs_notimpl_bs_sm_1,
bs_notimpl_bs_sm_2,
bs_notimpl_bs_sm_4,
bs_notimpl_bs_sm_8,
/* set region */
rsbus_bs_sr_1,
rsbus_bs_sr_2,
bs_notimpl_bs_sr_4,
bs_notimpl_bs_sr_8,
/* copy */
bs_notimpl_bs_c_1,
bs_notimpl_bs_c_2,
bs_notimpl_bs_c_4,
bs_notimpl_bs_c_8,
};
/* bus space functions */
/* Rough-and-ready implementations from arm26 */
void
rsbus_bs_rr_1(void *cookie, bus_space_handle_t bsh,
bus_size_t offset, u_int8_t *datap, bus_size_t count)
{
int i;
for (i = 0; i < count; i++)
datap[i] = rsbus_bs_r_1(cookie, bsh, offset + i);
}
void
rsbus_bs_rr_2(void *cookie, bus_space_handle_t bsh,
bus_size_t offset, u_int16_t *datap, bus_size_t count)
{
int i;
for (i = 0; i < count; i++)
datap[i] = rsbus_bs_r_2(cookie, bsh, offset + i);
}
void
rsbus_bs_wr_1(void *cookie, bus_space_handle_t bsh,
bus_size_t offset, u_int8_t const *datap,
bus_size_t count)
{
int i;
for (i = 0; i < count; i++)
rsbus_bs_w_1(cookie, bsh, offset + i, datap[i]);
}
void
rsbus_bs_wr_2(void *cookie, bus_space_handle_t bsh,
bus_size_t offset, u_int16_t const *datap,
bus_size_t count)
{
int i;
for (i = 0; i < count; i++)
rsbus_bs_w_2(cookie, bsh, offset + i, datap[i]);
}
void
rsbus_bs_sr_1(void *cookie, bus_space_handle_t bsh,
bus_size_t offset, u_int8_t value, bus_size_t count)
{
int i;
for (i = 0; i < count; i++)
rsbus_bs_w_1(cookie, bsh, offset + i, value);
}
void
rsbus_bs_sr_2(void *cookie, bus_space_handle_t bsh,
bus_size_t offset, u_int16_t value, bus_size_t count)
{
int i;
for (i = 0; i < count; i++)
rsbus_bs_w_2(cookie, bsh, offset + i, value);
}

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sys/arch/acorn32/eb7500atx/rsbus_io_asm.S Normal file
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/* $NetBSD: rsbus_io_asm.S,v 1.1 2004/01/03 14:31:28 chris Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <machine/asm.h>
/*
* bus_space I/O functions for rsbus
*/
/*
* read single
*/
ENTRY(rsbus_bs_r_1)
mov r2, r2, lsl r0
ldrb r0, [r1, r2]
mov pc, lr
ENTRY(rsbus_bs_r_2)
mov r2, r2, lsl r0
ldr r0, [r1, r2]
bic r0, r0, #0xff000000
bic r0, r0, #0x00ff0000
mov pc, lr
ENTRY(rsbus_bs_r_4)
mov r2, r2, lsl r0
ldr r0, [r1, r2]
mov pc, lr
/*
* write single
*/
ENTRY(rsbus_bs_w_1)
mov r2, r2, lsl r0
strb r3, [r1, r2]
mov pc, lr
ENTRY(rsbus_bs_w_2)
mov r3, r3, lsl #16
orr r3, r3, r3, lsr #16
mov r2, r2, lsl r0
str r3, [r1, r2]
mov pc, lr
ENTRY(rsbus_bs_w_4)
mov r2, r2, lsl r0
str r3, [r1, r2]
mov pc, lr
/*
* read multiple
*/
ENTRY(rsbus_bs_rm_1)
add r0, r1, r2, lsl r0
ldr r2, [sp, #0]
/* Make sure that we have a positive length */
cmp r2, #0x00000000
movle pc, lr
rsbus_rm_1_loop:
ldrb r1, [r0]
strb r1, [r3], #0x0001
subs r2, r2, #0x00000001
bgt rsbus_rm_1_loop
mov pc, lr
ENTRY(rsbus_bs_rm_2)
add r0, r1, r2, lsl r0
mov r1, r3
ldr r2, [sp, #0]
b _C_LABEL(insw)
/*
* write multiple
*/
ENTRY(rsbus_bs_wm_1)
add r0, r1, r2, lsl r0
ldr r2, [sp, #0]
/* Make sure that we have a positive length */
cmp r2, #0x00000000
movle pc, lr
rsbus_wm_1_loop:
ldrb r1, [r3], #0x0001
strb r1, [r0]
subs r2, r2, #0x00000001
bgt rsbus_wm_1_loop
mov pc, lr
ENTRY(rsbus_bs_wm_2)
add r0, r1, r2, lsl r0
mov r1, r3
ldr r2, [sp, #0]
b _C_LABEL(outsw)

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sys/arch/acorn32/eb7500atx/rside.c Normal file
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/* $NetBSD: rside.c,v 1.1 2004/01/03 14:31:28 chris Exp $ */
/*
* Copyright (c) 1997-1998 Mark Brinicombe
* Copyright (c) 1997-1998 Causality Limited
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/conf.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <machine/intr.h>
#include <machine/io.h>
#include <machine/bus.h>
#include <acorn32/eb7500atx/rsidereg.h>
#include <machine/irqhandler.h>
#include <dev/ata/atavar.h>
#include <dev/ic/wdcvar.h>
#include <acorn32/eb7500atx/rsbus.h>
/*
* RiscStation IDE device.
*
* This probes and attaches the top level IDE device to the rsbus.
* It then configures any children of the IDE device.
* The attach args specify whether it is configuring the primary or
* secondary channel.
* The children are expected to be wdc devices using rside attachments.
*
* The hardware notes are:
* Two ide ports are fitted, each with registers spaced 0x40 bytes apart
* with the extra control register at offset 0x380 from the base of the
* port.
*
* Primary:
* Registers at 0x302b800 (nPCCS1 + 0x0)
* IRQ connected to nEvent1 (IRQ register D)
*
* Secondary:
* Registers at 0x302bc00 (nPCCS1 + 0x400)
* IRQ connected to nEvent2 (IRQ register D)
*
* PIO timings can be changed by modifying the access speed register in the
* IOMD, as there is nothing else in the nPCCS1 space.
*
* The Reset line is asserted by unsetting bit 4 in IO register
* IOMD + 0x121CC.
*/
/*
* make a private tag so that we can use mainbus's map/unmap
*/
static struct bus_space rside_bs_tag;
/*
* RiscStation IDE card softc structure.
*
* Contains the device node, podule information and global information
* required by the driver such as the card version and the interrupt mask.
*/
struct rside_softc {
struct wdc_softc sc_wdcdev; /* common wdc definitions */
struct wdc_channel *wdc_chanarray[2]; /* channels definition */
struct rside_channel {
struct wdc_channel wdc_channel; /* generic part */
struct ata_queue wdc_chqueue; /* channel queue */
irqhandler_t *wdc_ih; /* interrupt handler */
} rside_channels[2];
};
int rside_probe __P((struct device *, struct cfdata *, void *));
void rside_attach __P((struct device *, struct device *, void *));
CFATTACH_DECL(rside, sizeof(struct rside_softc),
rside_probe, rside_attach, NULL, NULL);
/*
* Create an array of address structures. These define the addresses and
* masks needed for the different channels.
*
* index = channel
*/
struct {
u_int drive_registers;
u_int aux_register;
} rside_info[] = {
{ PRIMARY_DRIVE_REGISTERS_POFFSET, PRIMARY_AUX_REGISTER_POFFSET,
},
{ SECONDARY_DRIVE_REGISTERS_POFFSET, SECONDARY_AUX_REGISTER_POFFSET,
}
};
/*
* Card probe function
*/
int
rside_probe(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
/* if we're including this, then for now assume it exists */
return 1;
}
/*
* Card attach function
*
* Identify the card version and configure any children.
*/
void
rside_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct rside_softc *sc = (void *)self;
struct rsbus_attach_args *rs = (void *)aux;
int channel, i;
struct rside_channel *scp;
struct wdc_channel *cp;
printf("\n");
/*
* we need our own bus tag as the register spacing
* is not the default.
*
* For the rsbus the bus tag cookie is the shift
* to apply to registers
* So duplicate the bus space tag and change the
* cookie.
*/
rside_bs_tag = *rs->sa_iot;
rside_bs_tag.bs_cookie = (void *) DRIVE_REGISTER_SPACING_SHIFT;
/* Fill in wdc and channel infos */
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16;
sc->sc_wdcdev.PIO_cap = 0;
sc->sc_wdcdev.DMA_cap = 0;
sc->sc_wdcdev.UDMA_cap = 0;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = 2;
for (channel = 0 ; channel < 2; channel++) {
scp = &sc->rside_channels[channel];
sc->wdc_chanarray[channel] = &scp->wdc_channel;
cp = &scp->wdc_channel;
cp->channel = channel;
cp->wdc = &sc->sc_wdcdev;
cp->ch_queue = &scp->wdc_chqueue;
cp->cmd_iot = cp->ctl_iot = &rside_bs_tag;
if (bus_space_map(cp->cmd_iot,
rside_info[channel].drive_registers,
DRIVE_REGISTERS_SPACE, 0, &cp->cmd_baseioh))
panic("couldn't map drive registers channel = %d,"
"registers@0x08%x\n",
channel, rside_info[channel].drive_registers);
for (i = 0; i < WDC_NREG; i++) {
if (bus_space_subregion(cp->cmd_iot, cp->cmd_baseioh,
i * (DRIVE_REGISTER_BYTE_SPACING >> 2), 4,
&cp->cmd_iohs[i]) != 0) {
bus_space_unmap(cp->cmd_iot, cp->cmd_baseioh,
DRIVE_REGISTERS_SPACE);
continue;
}
}
if (bus_space_map(cp->ctl_iot,
rside_info[channel].aux_register, 0x4, 0, &cp->ctl_ioh))
{
bus_space_unmap(cp->cmd_iot, cp->cmd_baseioh,
DRIVE_REGISTERS_SPACE);
continue;
}
/* attach it to the interrupt */
if ((scp->wdc_ih = intr_claim((channel == 0 ? IRQ_NEVENT1 : IRQ_NEVENT2), IPL_BIO,
"rside", wdcintr, cp)) == NULL)
panic("%s: Cannot claim interrupt %d\n",
self->dv_xname, (channel == 0 ? IRQ_NEVENT1 : IRQ_NEVENT2));
wdcattach(cp);
}
}

52
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/* $NetBSD: rsidereg.h,v 1.1 2004/01/03 14:31:28 chris Exp $ */
/*
* Copyright (c) 2002 Chris Gilbert
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Thanks to Gareth Simpson, Simtec Electronics for providing
* the hardware information.
*/
/*
* Registers and address offsets for the Simtec IDE card.
*/
/* IDE drive registers */
#define PRIMARY_DRIVE_REGISTERS_POFFSET 0x0302b800
#define PRIMARY_AUX_REGISTER_POFFSET (PRIMARY_DRIVE_REGISTERS_POFFSET + 0x380)
#define SECONDARY_DRIVE_REGISTERS_POFFSET 0x0302bc00
#define SECONDARY_AUX_REGISTER_POFFSET (SECONDARY_DRIVE_REGISTERS_POFFSET + 0x380)
#define DRIVE_REGISTERS_SPACE (8 * 0x40)
#define DRIVE_REGISTER_BYTE_SPACING (0x40)
#define DRIVE_REGISTER_SPACING_SHIFT 6
/* Other registers */
#define CONTROL_SECONDARY_IRQ IRQ_NEVENT1
#define CONTROL_PRIMARY_IRQ IRQ_NEVENT2