292 lines
8.0 KiB
C
292 lines
8.0 KiB
C
/* $NetBSD: adm5120_intr.c,v 1.7 2016/08/26 15:45:48 skrll Exp $ */
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/*-
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* Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* 3. The names of the authors may not be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Platform-specific interrupt support for the Alchemy Semiconductor Pb1000.
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*
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* The Alchemy Semiconductor Pb1000's interrupts are wired to two internal
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* interrupt controllers.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: adm5120_intr.c,v 1.7 2016/08/26 15:45:48 skrll Exp $");
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#include "opt_ddb.h"
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#define __INTR_PRIVATE
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#include <sys/param.h>
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#include <sys/intr.h>
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#include <sys/malloc.h>
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#include <mips/locore.h>
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#include <mips/adm5120/include/adm5120reg.h>
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#include <mips/adm5120/include/adm5120var.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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/*
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* This is a mask of bits to clear in the SR when we go to a
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* given hardware interrupt priority level.
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*/
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static const struct ipl_sr_map adm5120_ipl_sr_map = {
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.sr_bits = {
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[IPL_NONE] = 0,
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[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
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[IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0,
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[IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
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[IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK,
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[IPL_VM] = MIPS_SOFT_INT_MASK|MIPS_INT_MASK_0,
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[IPL_SCHED] = MIPS_INT_MASK,
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[IPL_HIGH] = MIPS_INT_MASK,
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},
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};
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#define NIRQS 32
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const char * const adm5120_intrnames[NIRQS] = {
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"timer", /* 0 */
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"uart0", /* 1 */
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"uart1", /* 2 */
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"usb", /* 3 */
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"intx0/gpio2", /* 4 */
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"intx1/gpio4", /* 5 */
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"pci0", /* 6 */
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"pci1", /* 7 */
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"pci2", /* 8 */
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"switch",/* 9 */
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"res10", /* 10 */
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"res11", /* 11 */
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"res12", /* 12 */
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"res13", /* 13 */
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"res14", /* 14 */
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"res15", /* 15 */
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"res16", /* 16 */
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"res17", /* 17 */
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"res18", /* 18 */
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"res19", /* 19 */
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"res20", /* 20 */
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"res21", /* 21 */
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"res22", /* 22 */
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"res23", /* 23 */
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"res24", /* 24 */
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"res25", /* 25 */
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"res26", /* 26 */
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"res27", /* 27 */
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"res28", /* 28 */
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"res29", /* 29 */
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"res30", /* 30 */
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"res31", /* 31 */
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};
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struct adm5120_intrhead {
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struct evcnt intr_count;
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int intr_refcnt;
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};
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struct adm5120_intrhead adm5120_intrtab[NIRQS];
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#define NINTRS 2 /* MIPS INT0 - INT1 */
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struct adm5120_cpuintr {
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LIST_HEAD(, evbmips_intrhand) cintr_list;
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struct evcnt cintr_count;
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};
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struct adm5120_cpuintr adm5120_cpuintrs[NINTRS];
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const char * const adm5120_cpuintrnames[NINTRS] = {
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"int 0 (irq)",
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"int 1 (fiq)",
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};
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#define REG_READ(o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(ADM5120_BASE_ICU + (o)))
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#define REG_WRITE(o,v) (REG_READ(o)) = (v)
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void
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evbmips_intr_init(void)
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{
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ipl_sr_map = adm5120_ipl_sr_map;
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for (size_t i = 0; i < NINTRS; i++) {
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LIST_INIT(&adm5120_cpuintrs[i].cintr_list);
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evcnt_attach_dynamic(&adm5120_cpuintrs[i].cintr_count,
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EVCNT_TYPE_INTR, NULL, "mips", adm5120_cpuintrnames[i]);
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}
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for (size_t i = 0; i < NIRQS; i++) {
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/* XXX steering - use an irqmap array? */
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adm5120_intrtab[i].intr_refcnt = 0;
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evcnt_attach_dynamic(&adm5120_intrtab[i].intr_count,
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EVCNT_TYPE_INTR, NULL, "adm5120", adm5120_intrnames[i]);
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}
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/* disable all interrupts */
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REG_WRITE(ICU_DISABLE_REG, ICU_INT_MASK);
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}
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void *
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adm5120_intr_establish(int irq, int priority, int (*func)(void *), void *arg)
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{
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struct evbmips_intrhand *ih;
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uint32_t irqmask;
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int cpu_int, s;
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if (irq < 0 || irq >= NIRQS)
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panic("adm5120_intr_establish: bogus IRQ %d", irq);
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ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
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if (ih == NULL)
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return NULL;
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ih->ih_func = func;
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ih->ih_arg = arg;
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ih->ih_irq = irq;
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s = splhigh();
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/*
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* First, link it into the tables.
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* XXX do we want a separate list (really, should only be one item, not
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* a list anyway) per irq, not per CPU interrupt?
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*/
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cpu_int = (priority == INTR_FIQ) ? 1 : 0;
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LIST_INSERT_HEAD(&adm5120_cpuintrs[cpu_int].cintr_list, ih, ih_q);
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/*
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* Now enable it.
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*/
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if (adm5120_intrtab[irq].intr_refcnt++ == 0) {
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irqmask = 1 << irq;
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/* configure as IRQ or FIQ */
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if (priority == INTR_FIQ) {
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REG_WRITE(ICU_MODE_REG,
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REG_READ(ICU_MODE_REG) | irqmask);
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} else {
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REG_WRITE(ICU_MODE_REG,
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REG_READ(ICU_MODE_REG) & ~irqmask);
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}
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/* enable */
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REG_WRITE(ICU_ENABLE_REG, irqmask);
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}
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splx(s);
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return ih;
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}
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void
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adm5120_intr_disestablish(void *cookie)
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{
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struct evbmips_intrhand *ih = cookie;
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int irq, s;
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uint32_t irqmask;
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irq = ih->ih_irq;
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s = splhigh();
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/*
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* First, remove it from the table.
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*/
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LIST_REMOVE(ih, ih_q);
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/*
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* Now, disable it, if there is nothing remaining on the
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* list.
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*/
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if (adm5120_intrtab[irq].intr_refcnt-- == 1) {
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irqmask = 1 << irq; /* only used as a mask from here on */
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/* disable this irq in HW */
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REG_WRITE(ICU_DISABLE_REG, irqmask);
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}
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splx(s);
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free(ih, M_DEVBUF);
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}
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void
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evbmips_iointr(int ipl, uint32_t ipending, struct clockframe *cf)
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{
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struct evbmips_intrhand *ih;
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uint32_t irqmask, irqstat;
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for (int level = NINTRS - 1; level >= 0; level--) {
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if ((ipending & (MIPS_INT_MASK_0 << level)) == 0)
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continue;
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if (level)
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irqstat = REG_READ(ICU_FIQ_STATUS_REG);
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else
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irqstat = REG_READ(ICU_STATUS_REG);
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adm5120_cpuintrs[level].cintr_count.ev_count++;
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LIST_FOREACH(ih, &adm5120_cpuintrs[level].cintr_list, ih_q) {
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irqmask = 1 << ih->ih_irq;
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if (irqmask & irqstat) {
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adm5120_intrtab[ih->ih_irq].intr_count.ev_count++;
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(*ih->ih_func)(ih->ih_arg);
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}
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}
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}
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}
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