simonb 5b6caeca74 Mark the Au1x00 CPUs as having a fully coherent data cache that doesn't ... require flushing (even in the instruction cache handlers). This gives about a 4% improvement in a "make depend" benchmark. Mark the SB-1 CPUs as having a fully coherent data cache that only require flushing in the instruction cache handlers. This gives about a 5% improvement in a "make depend" benchmark.		2002-12-17 12:07:50 +00:00
..
alchemy	Fix typo in the address of the Au1500 MAC1 enable register; 2nd MAC works	2002-11-17 04:57:34 +00:00
bonito	Update to rev 1.48 from Algorithmics; adds BONITO64 register definitions.	2002-08-18 16:00:33 +00:00
cfe	update to latest CFE API code	2002-11-08 19:35:38 +00:00
conf	Remove the explicit `makeoptions MACHINE_ARCH="mipse{b,l}"' for kernel	2002-12-09 22:54:09 +00:00
include	Add support for caches where the data cache is fully coherent, and	2002-12-17 12:04:29 +00:00
mips	Mark the Au1x00 CPUs as having a fully coherent data cache that doesn't	2002-12-17 12:07:50 +00:00
sibyte	initial support for mac features in new chip revs	2002-11-19 01:44:04 +00:00
Makefile	Install the kernel linker script in /usr/lkm/ldscript so that modload(8)	2002-10-10 01:59:29 +00:00
Makefile.inc