junyoung 281fa073dc Display the extended feature flags with non-Intel processors rather than ... the standard flags. See also PR#19163. Before: cpu0: AMD Athlon XP 1800+ (686-class), 1532.11 MHz cpu0: features 383f9ff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,SEP,MTRR> cpu0: features 383f9ff<PGE,MCA,CMOV,FGPAT,PSE36,MMX> cpu0: features 383f9ff<FXSR,SSE> After: cpu0: AMD Athlon XP 1800+ (686-class), 1532.11 MHz cpu0: features c3cbf9ff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,SEP,MTRR> cpu0: features c3cbf9ff<PGE,MCA,CMOV,PAT,PSE36,MPC,MMXX,MMX> cpu0: features c3cbf9ff<FXSR,SSE,3DNOW2,3DNOW> While I'm here, amd_cpuid_cpu_cacheinfo() is an info function rather than a probe function.		2002-12-06 02:38:25 +00:00
..
acpi	Get this to compile again in the ioapic case.	2002-11-22 16:16:56 +00:00
bios	Tidy up CFATTACH_DECL() formatting.	2002-10-02 05:47:08 +00:00
bioscall	Rebuild after my re-arrangement of GDT entries, since this code depends on	2002-01-23 15:05:33 +00:00
compile
conf	add IEEE1394 configuration(Comment out)	2002-12-05 09:32:22 +00:00
eisa	New interrupt code. The basic idea behind it is to hide the differences	2002-11-22 15:23:35 +00:00
gdbscripts
i386	Display the extended feature flags with non-Intel processors rather than	2002-12-06 02:38:25 +00:00
include	Display the extended feature flags with non-Intel processors rather than	2002-12-06 02:38:25 +00:00
isa	Don't use delay() in the IPI wait loop. Use an empty one instead, with	2002-12-04 01:36:10 +00:00
mca	New interrupt code. The basic idea behind it is to hide the differences	2002-11-22 15:23:35 +00:00
pci	New interrupt code. The basic idea behind it is to hide the differences	2002-11-22 15:23:35 +00:00
pnpbios	Provide a cast when setting up the interrupt handler (npxintr has a different	2002-11-24 10:19:37 +00:00
stand	If booting from floppy in 2.88MB drive, actually test if it's possible	2002-12-04 18:26:56 +00:00
Makefile