Display the extended feature flags with non-Intel processors rather than
the standard flags. See also PR#19163. Before: cpu0: AMD Athlon XP 1800+ (686-class), 1532.11 MHz cpu0: features 383f9ff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,SEP,MTRR> cpu0: features 383f9ff<PGE,MCA,CMOV,FGPAT,PSE36,MMX> cpu0: features 383f9ff<FXSR,SSE> After: cpu0: AMD Athlon XP 1800+ (686-class), 1532.11 MHz cpu0: features c3cbf9ff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,SEP,MTRR> cpu0: features c3cbf9ff<PGE,MCA,CMOV,PAT,PSE36,MPC,MMXX,MMX> cpu0: features c3cbf9ff<FXSR,SSE,3DNOW2,3DNOW> While I'm here, amd_cpuid_cpu_cacheinfo() is an info function rather than a probe function.
This commit is contained in:
junyoung
parent
7ae2f112dd
commit
281fa073dc
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.500 2002/12/05 16:19:08 junyoung Exp $ */
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/* $NetBSD: machdep.c,v 1.501 2002/12/06 02:38:25 junyoung Exp $ */
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/*-
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* Copyright (c) 1996, 1997, 1998, 2000 The NetBSD Foundation, Inc.
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@ -76,7 +76,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.500 2002/12/05 16:19:08 junyoung Exp $");
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.501 2002/12/06 02:38:25 junyoung Exp $");
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#include "opt_cputype.h"
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#include "opt_ddb.h"
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@ -341,6 +341,7 @@ void winchip_cpu_setup __P((struct cpu_info *));
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void amd_family5_setup __P((struct cpu_info *));
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void transmeta_cpu_setup __P((struct cpu_info *));
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static void via_cpu_probe __P((struct cpu_info *));
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static void amd_family6_probe __P((struct cpu_info *));
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static void transmeta_cpu_info __P((struct cpu_info *));
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@ -792,8 +793,8 @@ const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = {
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"K5 or K6" /* Default */
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},
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amd_family5_setup,
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amd_cpuid_cpu_cacheinfo,
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NULL,
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amd_cpuid_cpu_cacheinfo,
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},
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/* Family 6 */
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{
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@ -818,7 +819,7 @@ const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = {
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"Unknown K7 (Athlon)" /* Default */
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},
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NULL,
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amd_cpuid_cpu_cacheinfo,
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NULL,
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NULL,
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} }
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},
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@ -969,7 +970,7 @@ const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = {
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"C3" /* Default */
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},
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NULL,
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NULL,
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via_cpu_probe,
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NULL,
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},
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/* Family > 6, not yet available from VIA */
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@ -1098,6 +1099,29 @@ winchip_cpu_setup(ci)
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: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
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: "a" (code));
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void
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via_cpu_probe(struct cpu_info *ci)
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{
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u_int descs[4];
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u_int lfunc;
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/*
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* Determine the largest extended function value.
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*/
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CPUID(0x80000000, descs[0], descs[1], descs[2], descs[3]);
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lfunc = descs[0];
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/*
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* Determine the extended feature flags.
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*/
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if (lfunc >= 0x80000001) {
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CPUID(0x80000001, descs[0], descs[1], descs[2], descs[3]);
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ci->ci_feature_flags = descs[3];
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ci->ci_feature_str2 = CPUID_EXT_FLAGS2;
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ci->ci_feature_str3 = CPUID_EXT_FLAGS3;
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}
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}
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static void
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cpu_probe_base_features(struct cpu_info *ci)
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{
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@ -1121,6 +1145,13 @@ cpu_probe_base_features(struct cpu_info *ci)
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CPUID(1, ci->ci_signature, miscbytes, dummy1, ci->ci_feature_flags);
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/*
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* These may be overridden with vendor specific strings later.
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*/
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ci->ci_feature_str1 = CPUID_FLAGS1;
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ci->ci_feature_str2 = CPUID_FLAGS2;
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ci->ci_feature_str3 = CPUID_FLAGS3;
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/* Brand is low order 8 bits of ebx */
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ci->ci_brand_id = miscbytes & 0xff;
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@ -1213,14 +1244,25 @@ cpu_probe_features(struct cpu_info *ci)
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void
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amd_family6_probe(struct cpu_info *ci)
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{
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u_int32_t eax;
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u_int32_t dummy1, dummy2, dummy3;
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u_int32_t lfunc;
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u_int32_t descs[4];
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u_int32_t brand[12];
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char *p;
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int i;
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CPUID(0x80000000, eax, dummy1, dummy2, dummy3);
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if (eax < 0x80000004)
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CPUID(0x80000000, lfunc, descs[1], descs[2], descs[3]);
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/*
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* Determine the extended feature flags.
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*/
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if (lfunc >= 0x80000001) {
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CPUID(0x80000001, descs[0], descs[1], descs[2], descs[3]);
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ci->ci_feature_flags |= descs[3];
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ci->ci_feature_str2 = CPUID_EXT_FLAGS2;
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ci->ci_feature_str3 = CPUID_EXT_FLAGS3;
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}
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if (lfunc < 0x80000004)
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return;
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CPUID(0x80000002, brand[0], brand[1], brand[2], brand[3]);
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@ -1795,18 +1837,18 @@ identifycpu(struct cpu_info *ci)
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if (ci->ci_feature_flags) {
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if ((ci->ci_feature_flags & CPUID_MASK1) != 0) {
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bitmask_snprintf(ci->ci_feature_flags, CPUID_FLAGS1,
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buf, sizeof(buf));
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bitmask_snprintf(ci->ci_feature_flags,
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ci->ci_feature_str1, buf, sizeof(buf));
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printf("%s: features %s\n", cpuname, buf);
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}
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if ((ci->ci_feature_flags & CPUID_MASK2) != 0) {
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bitmask_snprintf(ci->ci_feature_flags, CPUID_FLAGS2,
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buf, sizeof(buf));
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bitmask_snprintf(ci->ci_feature_flags,
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ci->ci_feature_str2, buf, sizeof(buf));
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printf("%s: features %s\n", cpuname, buf);
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}
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if ((ci->ci_feature_flags & CPUID_MASK3) != 0) {
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bitmask_snprintf(ci->ci_feature_flags, CPUID_FLAGS3,
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buf, sizeof(buf));
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bitmask_snprintf(ci->ci_feature_flags,
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ci->ci_feature_str3, buf, sizeof(buf));
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printf("%s: features %s\n", cpuname, buf);
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}
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.h,v 1.90 2002/11/28 21:43:55 fvdl Exp $ */
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/* $NetBSD: cpu.h,v 1.91 2002/12/06 02:38:27 junyoung Exp $ */
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/*-
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* Copyright (c) 1990 The Regents of the University of California.
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@ -127,6 +127,9 @@ struct cpu_info {
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int32_t ci_cpuid_level;
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u_int32_t ci_signature; /* X86 cpuid type */
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u_int32_t ci_feature_flags;/* X86 CPUID feature bits */
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char * ci_feature_str1; /* Vendor specific feature strings */
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char * ci_feature_str2;
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char * ci_feature_str3;
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u_int32_t ci_cpu_class; /* CPU class */
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u_int32_t ci_brand_id; /* Intel brand id */
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u_int32_t ci_vendor[4]; /* vendor string */
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@ -1,4 +1,4 @@
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/* $NetBSD: specialreg.h,v 1.25 2002/12/05 17:25:26 junyoung Exp $ */
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/* $NetBSD: specialreg.h,v 1.26 2002/12/06 02:38:28 junyoung Exp $ */
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/*-
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* Copyright (c) 1991 The Regents of the University of California.
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@ -133,6 +133,20 @@
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#define CPUID_FLAGS3 "\20\31FXSR\32SSE\33SSE2\34SS\35HTT\36TM\37B30\40SBF"
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#define CPUID_MASK3 0xff000000
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/*
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* AMD/VIA processor specific flags.
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*/
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#define CPUID_MPC 0x00080000 /* Multiprocessing Capable */
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#define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */
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#define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */
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#define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */
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#define CPUID_EXT_FLAGS2 "\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN" \
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"\24MPC\25B20\26B21\27MMXX\30MMX"
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#define CPUID_EXT_FLAGS3 "\20\31FXSR\32SSE\33B26\34B27\35B28\36B29" \
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"\0373DNOW2\0403DNOW"
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#define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 15)
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#define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 15)
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#define CPUID2STEPPING(cpuid) ((cpuid) & 15)
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