sekiya 8f1c003137 Set mips_sdcache_forceinv to 1 for r5k processors. ... We now support secondary cache operation on r5ksc out-of-the-box.		2005-03-01 04:25:00 +00:00
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arcemu.c
arcemu.h
autoconf.c
bus.c
clock.c
clockvar.h
console.c
cpu.c
disksubr.c
ip22_cache.S
locore_machdep.S
machdep.c	Set mips_sdcache_forceinv to 1 for r5k processors.	2005-03-01 04:25:00 +00:00
mainbus.c