thorpej 636e9cd08b Add a "cacheline_size" argument to pci_configure_bus(). It is used ... to set the cacheline size in the BHLC register. This should be the size of the largest D-cache line on a system.		2001-11-28 23:48:34 +00:00
..
bonito_mainbus.c	Print more BONITO rev. info.	2001-06-25 20:15:57 +00:00
com_mainbus.c	Yet more interrupt cleanup -- the platform mater interrupt establish	2001-06-15 04:01:39 +00:00
lpt_mainbus.c	Yet more interrupt cleanup -- the platform mater interrupt establish	2001-06-15 04:01:39 +00:00
mainbus.c	Add a "cacheline_size" argument to pci_configure_bus(). It is used	2001-11-28 23:48:34 +00:00
mcclock.c	Rewrite the interrupt handling code:	2001-06-10 05:26:58 +00:00
mcclock_mainbus.c	Add support for the Algorithmics P-4032 board. This is totally	2001-06-01 16:00:03 +00:00
mcclockvar.h	…
vtpbc_mainbus.c	A P-6032 will never have a V3 PBC -- don't include its option header.	2001-06-22 03:45:24 +00:00