Add support for the Algorithmics P-4032 board. This is totally

untested, since I have no P-4032 board, but it's no worse than
the current situation, which is "totally non-working P-4032
support in the ARC port, of all places".
This commit is contained in:
thorpej 2001-06-01 16:00:03 +00:00
parent 23a3dc1508
commit 71cb790fb5
16 changed files with 1817 additions and 24 deletions

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/* $NetBSD: algor_p4032_bus_io.c,v 1.1 2001/06/01 16:00:03 thorpej Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Platform-specific PCI bus I/O support for the Algorithmics P-4032.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/syslog.h>
#include <sys/device.h>
#include <uvm/uvm_extern.h>
#include <machine/locore.h>
#include <algor/algor/algor_p4032reg.h>
#include <algor/algor/algor_p4032var.h>
#define CHIP algor_p4032
#define CHIP_EX_MALLOC_SAFE(v) (((struct p4032_config *)(v))->ac_mallocsafe)
#define CHIP_IO_EXTENT(v) (((struct p4032_config *)(v))->ac_io_ex)
/* IO region 1 */
#define CHIP_IO_W1_BUS_START(v) 0x00000000UL
#define CHIP_IO_W1_BUS_END(v) 0x000fffffUL
#define CHIP_IO_W1_SYS_START(v) P4032_PCIIO
#define CHIP_IO_W1_SYS_END(v) (P4032_PCIIO + CHIP_IO_W1_BUS_END(v))
#include <algor/pci/pci_alignstride_bus_io_chipdep.c>

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/* $NetBSD: algor_p4032_bus_locio.c,v 1.1 2001/06/01 16:00:03 thorpej Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Platform-specific local bus I/O support for the Algorithmics P-4032.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/syslog.h>
#include <sys/device.h>
#include <uvm/uvm_extern.h>
#include <machine/locore.h>
#include <algor/algor/algor_p4032reg.h>
#include <algor/algor/algor_p4032var.h>
#define CHIP algor_p4032loc
/* log2(4) */
#define CHIP_ALIGN_STRIDE 2
/* IO region 1 */
#define CHIP_IO_W1_BUS_START(v) 0x00000000UL
#define CHIP_IO_W1_BUS_END(v) 0xffffffffUL
#define CHIP_IO_W1_SYS_START(v) 0
#define CHIP_IO_W1_SYS_END(v) CHIP_IO_W1_BUS_END(v)
#include <algor/pci/pci_alignstride_bus_io_chipdep.c>

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/* $NetBSD: algor_p4032_bus_mem.c,v 1.1 2001/06/01 16:00:03 thorpej Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Platform-specific PCI bus memory support for the Algorithmics P-4032.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/syslog.h>
#include <sys/device.h>
#include <uvm/uvm_extern.h>
#include <machine/locore.h>
#include <algor/algor/algor_p4032reg.h>
#include <algor/algor/algor_p4032var.h>
#define CHIP algor_p4032
#define CHIP_EX_MALLOC_SAFE(v) (((struct p4032_config *)(v))->ac_mallocsafe)
#define CHIP_MEM_EXTENT(v) (((struct p4032_config *)(v))->ac_mem_ex)
/* MEM region 1 */
#define CHIP_MEM_W1_BUS_START(v) 0x00000000UL
#define CHIP_MEM_W1_BUS_END(v) 0x007fffffUL
#define CHIP_MEM_W1_SYS_START(v) P4032_ISAMEM
#define CHIP_MEM_W1_SYS_END(v) (P4032_ISAMEM + CHIP_MEM_W1_BUS_END(v))
/* MEM region 2 */
#define CHIP_MEM_W2_BUS_START(v) 0x01000000UL
#define CHIP_MEM_W2_BUS_END(v) 0x07ffffffUL
#define CHIP_MEM_W2_SYS_START(v) P4032_PCIMEM
#define CHIP_MEM_W2_SYS_END(v) (P4032_PCIMEM + 0x06ffffffUL)
#if 0 /* XXX Should implement access to this via TLB or 64-bit KSEG */
/* MEM region 3 */
#define CHIP_MEM_W3_BUS_START(v) 0x20000000UL
#define CHIP_MEM_W3_BUS_END(v) 0xffffffffUL
#define CHIP_MEM_W3_SYS_START(v) P4032_PCIMEM_HI
#define CHIP_MEM_W3_SYS_END(v) (P4032_PCIMEM_HI + 0xe0000000UL)
#endif
#include <algor/pci/pci_alignstride_bus_mem_chipdep.c>

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/* $NetBSD: algor_p4032_dma.c,v 1.1 2001/06/01 16:00:03 thorpej Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Platform-specific DMA support for the Algorithmics P-4032.
*/
#include <sys/param.h>
#define _ALGOR_BUS_DMA_PRIVATE
#include <machine/bus.h>
#include <algor/algor/algor_p4032reg.h>
#include <algor/algor/algor_p4032var.h>
void
algor_p4032_dma_init(struct p4032_config *acp)
{
bus_dma_tag_t t;
/*
* Initialize the DMA tag used for PCI DMA.
*/
t = &acp->ac_pci_dmat;
t->_cookie = acp;
t->_wbase = P4032_DMA_PCI_PCIBASE;
t->_physbase = P4032_DMA_PCI_PHYSBASE;
t->_wsize = P4032_DMA_PCI_SIZE;
t->_dmamap_create = _bus_dmamap_create;
t->_dmamap_destroy = _bus_dmamap_destroy;
t->_dmamap_load = _bus_dmamap_load;
t->_dmamap_load_mbuf = _bus_dmamap_load_mbuf;
t->_dmamap_load_uio = _bus_dmamap_load_uio;
t->_dmamap_load_raw = _bus_dmamap_load_raw;
t->_dmamap_unload = _bus_dmamap_unload;
t->_dmamap_sync = _bus_dmamap_sync;
t->_dmamem_alloc = _bus_dmamem_alloc;
t->_dmamem_free = _bus_dmamem_free;
t->_dmamem_map = _bus_dmamem_map;
t->_dmamem_unmap = _bus_dmamem_unmap;
t->_dmamem_mmap = _bus_dmamem_mmap;
}

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/* $NetBSD: algor_p4032_intr.c,v 1.1 2001/06/01 16:00:03 thorpej Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Platform-specific interrupt support for the Algorithmics P-4032.
*
* The Algorithmics P-4032 has an interrupt controller that is pretty
* flexible -- it can take an interrupt source and route it to an
* arbitrary MIPS CPU hardware interrupt pin.
*
* Unfortunately, there aren't enough source pins as inputs to the
* controller. It makes it difficult to share interrupts between
* devices that have different logical levels (BIO, NET, etc.).
*
* As a result, this code needs a lot of work -- needs to have the
* interrupts fully-virtualized -- I just wanted to get *something*
* working quickly. --thorpej@netbsd.org
*/
#include "opt_ddb.h"
#include <sys/param.h>
#include <sys/queue.h>
#include <sys/malloc.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <machine/bus.h>
#include <machine/autoconf.h>
#include <machine/intr.h>
#include <algor/algor/algor_p4032reg.h>
#include <algor/algor/algor_p4032var.h>
#include <algor/algor/clockvar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pciidereg.h>
#include <dev/pci/pciidevar.h>
#include <dev/isa/isavar.h>
#define REGVAL(x) *((__volatile u_int32_t *)(MIPS_PHYS_TO_KSEG1((x))))
#define IRQREG_8BIT 0
#define IRQREG_ERROR 1
#define IRQREG_PCI 2
#define NIRQREG 3
struct irqreg {
bus_addr_t addr;
u_int32_t val;
};
struct irqreg p4032_irqregs[NIRQREG] = {
{ P4032_IRR0, 0 },
{ P4032_IRR1, 0 },
{ P4032_IRR2, 0 },
};
#define NSTEERREG 3
struct irqreg p4032_irqsteer[NSTEERREG] = {
{ P4032_XBAR0, 0 },
{ P4032_XBAR1, 0 },
{ P4032_XBAR2, 0 },
};
struct intrhand {
LIST_ENTRY(intrhand) ih_q;
int (*ih_func)(void *);
void *ih_arg;
const struct p4032_irqmap *ih_irqmap;
};
struct intrhead {
LIST_HEAD(, intrhand) intr_q;
struct evcnt intr_count;
};
#define NINTRS 4 /* MIPS INT0 - INT3 */
struct intrhead p4032_intrtab[NINTRS];
const char *p4032_intrnames[NINTRS] = {
"int 0",
"int 1",
"int 2",
"int 3 (clock)",
};
const char *p4032_pci_intrnames[4] = {
"PCIIRQ 0",
"PCIIRQ 1",
"PCIIRQ 2",
"PCIIRQ 3",
};
struct evcnt p4032_pci_intrcount[4];
const struct p4032_irqmap p4032_pci_irqmap[4] = {
/* PCIIRQ 0 */
{ &p4032_pci_intrcount[0],
IRQREG_PCI, IRR2_PCIIRQ0,
2, 0 },
/* PCIIRQ 1 */
{ &p4032_pci_intrcount[1],
IRQREG_PCI, IRR2_PCIIRQ1,
2, 2 },
/* PCIIRQ 2 */
{ &p4032_pci_intrcount[2],
IRQREG_PCI, IRR2_PCIIRQ2,
2, 4 },
/* PCIIRQ 3 */
{ &p4032_pci_intrcount[3],
IRQREG_PCI, IRR2_PCIIRQ3,
2, 6 },
};
const char *p4032_8bit_intrnames[8] = {
"PCI ctlr",
"floppy",
"pckbc",
"com 1",
"com 2",
"centronics",
"gpio",
"rtc",
};
struct evcnt p4032_8bit_intrcount[8];
const struct p4032_irqmap p4032_8bit_irqmap[8] = {
{ &p4032_8bit_intrcount[0],
IRQREG_8BIT, IRR0_PCICTLR,
0, 0 },
{ &p4032_8bit_intrcount[1],
IRQREG_8BIT, IRR0_FLOPPY,
0, 2 },
{ &p4032_8bit_intrcount[2],
IRQREG_8BIT, IRR0_PCKBC,
0, 4 },
{ &p4032_8bit_intrcount[3],
IRQREG_8BIT, IRR0_COM1,
0, 6 },
{ &p4032_8bit_intrcount[4],
IRQREG_8BIT, IRR0_COM2,
1, 0 },
{ &p4032_8bit_intrcount[5],
IRQREG_8BIT, IRR0_LPT,
1, 2 },
{ &p4032_8bit_intrcount[6],
IRQREG_8BIT, IRR0_GPIO,
1, 4 },
{ &p4032_8bit_intrcount[7],
IRQREG_8BIT, IRR0_RTC,
1, 6 },
};
int algor_p4032_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
const char *algor_p4032_pci_intr_string(void *, pci_intr_handle_t);
const struct evcnt *algor_p4032_pci_intr_evcnt(void *, pci_intr_handle_t);
void *algor_p4032_pci_intr_establish(void *, pci_intr_handle_t, int,
int (*)(void *), void *);
void algor_p4032_pci_conf_interrupt(void *, int, int, int, int, int *);
void algor_p4032_init_clock_intr(void);
void algor_p4032_iointr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
void
algor_p4032_intr_init(struct p4032_config *acp)
{
int i;
for (i = 0; i < NIRQREG; i++)
REGVAL(p4032_irqregs[i].addr) = p4032_irqregs[i].val;
for (i = 0; i < NSTEERREG; i++)
REGVAL(p4032_irqsteer[i].addr) = p4032_irqsteer[i].val;
for (i = 0; i < NINTRS; i++) {
LIST_INIT(&p4032_intrtab[i].intr_q);
evcnt_attach_dynamic(&p4032_intrtab[i].intr_count,
EVCNT_TYPE_INTR, NULL, "mips", p4032_intrnames[i]);
}
for (i = 0; i < 4; i++)
evcnt_attach_dynamic(&p4032_pci_intrcount[i],
EVCNT_TYPE_INTR, NULL, "pci", p4032_pci_intrnames[i]);
for (i = 0; i < 8; i++)
evcnt_attach_dynamic(&p4032_8bit_intrcount[i],
EVCNT_TYPE_INTR, NULL, "8bit", p4032_8bit_intrnames[i]);
acp->ac_pc.pc_intr_v = NULL;
acp->ac_pc.pc_intr_map = algor_p4032_pci_intr_map;
acp->ac_pc.pc_intr_string = algor_p4032_pci_intr_string;
acp->ac_pc.pc_intr_evcnt = algor_p4032_pci_intr_evcnt;
acp->ac_pc.pc_intr_establish = algor_p4032_pci_intr_establish;
acp->ac_pc.pc_intr_disestablish = algor_p4032_intr_disestablish;
acp->ac_pc.pc_conf_interrupt = algor_p4032_pci_conf_interrupt;
acp->ac_pc.pc_pciide_compat_intr_establish = NULL;
algor_iointr = algor_p4032_iointr;
algor_init_clock_intr = algor_p4032_init_clock_intr;
}
void *
algor_p4032_intr_establish(const struct p4032_irqmap *irqmap, int level,
int (*func)(void *), void *arg)
{
struct intrhand *ih;
int s;
/*
* XXX SHARING OF INTERRUPTS OF DIFFERENT LEVELS ON THE
* XXX SAME PCIIRQ IS COMPLETELY BROKEN.
* XXX FIXME!!!!
*/
/*
* XXX REFERENCE COUNTING OF PCIIRQS IS COMPLETELY
* XXX BROKEN, MAKING IT IMPOSSIBLE TO IMPLEMENT
* XXX INTR_DISESTABLISH.
* XXX FIXME!!!!
*/
switch (level) {
case IPL_BIO:
level = 0;
break;
case IPL_NET:
level = 1;
break;
case IPL_TTY:
#if 0
case IPL_SERIAL: /* same as IPL_TTY */
#endif
level = 2;
break;
case IPL_CLOCK:
level = 3;
break;
default:
printf("algor_p4032_intr_establish: bad level %d\n", level);
return (NULL);
}
ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
if (ih == NULL)
return (NULL);
ih->ih_func = func;
ih->ih_arg = arg;
ih->ih_irqmap = irqmap;
s = splhigh();
/*
* First, link it into the interrupt table.
*/
LIST_INSERT_HEAD(&p4032_intrtab[level].intr_q, ih, ih_q);
/*
* Then, steer the interrupt to the intended MIPS interrupt line.
*/
p4032_irqsteer[irqmap->xbarreg].val &= ~(3 << irqmap->xbarshift);
p4032_irqsteer[irqmap->xbarreg].val |= (level << irqmap->xbarshift);
REGVAL(p4032_irqsteer[irqmap->xbarreg].addr) =
p4032_irqsteer[irqmap->xbarreg].val;
/*
* Now enable it.
*/
/* XXX XXX XXX */
if (p4032_irqregs[irqmap->irqreg].val & irqmap->irqbit)
printf("WARNING: IRQREG %d BIT 0x%02x ALREADY IN USE!\n",
irqmap->irqreg, irqmap->irqbit);
/* XXX XXX XXX */
p4032_irqregs[irqmap->irqreg].val |= irqmap->irqbit;
REGVAL(p4032_irqregs[irqmap->irqreg].addr) =
p4032_irqregs[irqmap->irqreg].val;
splx(s);
return (ih);
}
void
algor_p4032_intr_disestablish(void *v, void *cookie)
{
panic("algor_p4032_intr_disestablish: I'm totally broken.");
}
void
algor_p4032_init_clock_intr(void)
{
/* Steer the clock interrupt to MIPS INT3 */
p4032_irqsteer[1].val |= (3 << 6);
REGVAL(p4032_irqsteer[1].addr) = p4032_irqsteer[1].val;
/* Now enable it. */
p4032_irqregs[IRQREG_8BIT].val |= IRR0_RTC;
REGVAL(p4032_irqregs[IRQREG_8BIT].addr) =
p4032_irqregs[IRQREG_8BIT].val;
}
void
algor_p4032_iointr(u_int32_t status, u_int32_t cause, u_int32_t pc,
u_int32_t ipending)
{
struct intrhand *ih;
int level, i;
u_int32_t irr[NIRQREG];
/* Check for ERROR interrupts. */
if (ipending & MIPS_INT_MASK_4) {
irr[IRQREG_ERROR] = REGVAL(p4032_irqregs[IRQREG_ERROR].addr);
if (irr[IRQREG_ERROR] & IRR1_BUSERR)
printf("WARNING: Bus error\n");
if (irr[IRQREG_ERROR] & IRR1_POWERFAIL)
printf("WARNING: Power failure\n");
if (irr[IRQREG_ERROR] & IRR1_DEBUG) {
#ifdef DDB
printf("Debug switch -- entering debugger\n");
led_display('D','D','B',' ');
Debugger();
led_display('N','B','S','D');
#else
printf("Debug switch ignored -- "
"no debugger configured\n");
#endif
}
/* Clear them. */
REGVAL(p4032_irqregs[IRQREG_ERROR].addr) = irr[IRQREG_ERROR];
}
/* Do clock interrupts. */
if (ipending & MIPS_INT_MASK_3) {
struct clockframe cf;
/*
* XXX Hi, um, yah, we need to deal with
* XXX the floppy interrupt here, too.
*/
(*clockfns->cf_intrack)(clockdev);
cf.pc = pc;
cf.sr = status;
hardclock(&cf);
p4032_intrtab[3].intr_count.ev_count++;
p4032_8bit_intrcount[7].ev_count++;
/* Re-enable clock interrupts. */
cause &= ~MIPS_INT_MASK_3;
_splset(MIPS_SR_INT_IE | MIPS_INT_MASK_3);
}
/*
* Read the interrupt pending registers, mask them with the
* ones we have enabled, and service them in order of decreasing
* priority.
*/
for (i = 0; i < NIRQREG; i++) {
if (i == IRQREG_ERROR)
continue;
irr[i] = REGVAL(p4032_irqregs[i].addr) & p4032_irqregs[i].val;
}
for (level = 2; level >= 0; level--) {
if ((ipending & (MIPS_INT_MASK_0 << level)) == 0)
continue;
p4032_intrtab[level].intr_count.ev_count++;
for (ih = LIST_FIRST(&p4032_intrtab[level].intr_q);
ih != NULL; ih = LIST_NEXT(ih, ih_q)) {
if (irr[ih->ih_irqmap->irqreg] &
ih->ih_irqmap->irqbit) {
ih->ih_irqmap->irqcount->ev_count++;
(*ih->ih_func)(ih->ih_arg);
}
}
cause &= ~(MIPS_INT_MASK_0 << level);
}
/* Re-enable anything that we have processed. */
_splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK));
}
/*****************************************************************************
* PCI interrupt support
*****************************************************************************/
int
algor_p4032_pci_intr_map(struct pci_attach_args *pa,
pci_intr_handle_t *ihp)
{
static const int pciirqmap[6/*device*/][4/*pin*/] = {
{ 1, -1, -1, -1 }, /* 5: Ethernet */
{ 2, 3, 0, 1 }, /* 6: PCI slot 1 */
{ 3, 0, 1, 2 }, /* 7: PCI slot 2 */
{ 0, -1, -1, -1 }, /* 8: SCSI */
{ -1, -1, -1, -1 }, /* 9: not used */
{ 0, 1, 2, 3 }, /* 10: custom connector */
};
pcitag_t bustag = pa->pa_intrtag;
int buspin = pa->pa_intrpin;
pci_chipset_tag_t pc = pa->pa_pc;
int device, irq;
if (buspin == 0) {
/* No IRQ used. */
return (1);
}
if (buspin > 4) {
printf("algor_p4032_pci_intr_map: bad interrupt pin %d\n",
buspin);
return (1);
}
pci_decompose_tag(pc, bustag, NULL, &device, NULL);
if (device < 5 || device > 10) {
printf("algor_p4032_pci_intr_map: bad device %d\n",
device);
return (1);
}
irq = pciirqmap[device - 5][buspin - 1];
if (irq == -1) {
printf("algor_p4032_pci_intr_map: no mapping for "
"device %d pin %d\n", device, buspin);
return (1);
}
*ihp = irq;
return (0);
}
const char *
algor_p4032_pci_intr_string(void *v, pci_intr_handle_t ih)
{
if (ih > 3)
panic("algor_p4032_intr_string: bogus IRQ %ld\n", ih);
return (p4032_pci_intrnames[ih]);
}
const struct evcnt *
algor_p4032_pci_intr_evcnt(void *v, pci_intr_handle_t ih)
{
/* XXX */
return (NULL);
}
void *
algor_p4032_pci_intr_establish(void *v, pci_intr_handle_t ih, int level,
int (*func)(void *), void *arg)
{
if (ih > 3)
panic("algor_p4032_intr_establish: bogus IRQ %ld\n", ih);
return (algor_p4032_intr_establish(&p4032_pci_irqmap[ih],
level, func, arg));
}
void
algor_p4032_pci_conf_interrupt(void *v, int bus, int dev, int func, int swiz,
int *iline)
{
/*
* We actually don't need to do anything; everything is handled
* in pci_intr_map().
*/
*iline = 0;
}

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@ -0,0 +1,115 @@
/* $NetBSD: algor_p4032reg.h,v 1.1 2001/06/01 16:00:03 thorpej Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Memory map and register definitions for the Algorithmics P-4032.
*/
#define P4032_MEMORY 0x00000000UL /* onbord DRAM memory */
/* 256 MB */
#define P4032_ISAMEM 0x10000000UL /* ISA window of PCI memory */
/* 8MB */
#define P4032_PCIMEM 0x11000000UL /* PCI memory window */
/* 112MB */
#define P4032_PCIIO 0x1ed00000UL /* PCI I/O window */
/* 1MB */
#define P4032_PCICFG 0x1ee00000UL /* PCI config space */
/* 1MB */
#define P4032_V962PBC 0x1ef00000UL /* V962PBC PCI controller */
/* 64KB */
#define P4032_CFGBOOT_W 0x1fc00000UL /* configured bootstrap (W) */
/* 1MB or 512KB */
#define P4032_SOCKET_W 0x1fd00000UL /* socket EPROM (W) */
/* 512KB */
#define P4032_FLASH_W 0x1fe00000UL /* flash (W) */
/* 1MB */
#define P4032_RTC 0x1ff00000UL /* RTC */
#define P4032_PCKBC 0x1ff10000UL /* keyboard controller */
#define P4032_LED 0x1ff20010UL /* LED display (4reg) */
#define P4032_LCD 0x1ff30000UL /* LCD display */
#define P4032_GPIO 0x1ff40000UL /* General purpose I/O */
#define P4032_FDC 0x1ff807c0UL /* floppy controller */
#define P4032_GAME 0x1ff80800UL /* game port (unused) */
#define P4032_COM2 0x1ff80be0UL /* COM2 */
#define P4032_LPT 0x1ff80de0UL /* parallel port */
#define P4032_COM1 0x1ff80fe0UL /* COM1 */
#define P4032_IRR0 0x1ff90000UL /* interrupt req. 0 */
#define P4032_IRR1 0x1ff90004UL /* interrupt req. 1 */
#define P4032_IRR2 0x1ff90008UL /* interrupt req. 2 */
#define P4032_XBAR0 0x1ff9000cUL /* interrupt crossbar 0 */
#define P4032_XBAR1 0x1ff90010UL /* interrupt crossbar 1 */
#define P4032_XBAR2 0x1ff90014UL /* interrupt crossbar 2 */
#define P4032_VERSION 0x1ff9001cUL /* board version */
#define P4032_FLOPPY_DMA_ACK 0x1ffa0fd4UL /* floppy "DMA ACK" */
#define P4032_BOARD_CONFIG 0x1ffb0000UL /* board configuration */
#define P4032_DRAM_CONFIG 0x1ffc0000UL /* DRAM configuration */
#define P4032_OPTION 0x1ffd0000UL /* option register */
#define P4032_PCIMEM_HI 0x20000000UL /* PCI memory high window */
/* 3.5GB */
/* IRR0 (8-bit devices) */
#define IRR0_PCICTLR 0x01 /* PCI controller */
#define IRR0_FLOPPY 0x02 /* floppy controller */
#define IRR0_PCKBC 0x04 /* keyboard controller */
#define IRR0_COM1 0x08 /* COM1 */
#define IRR0_COM2 0x10 /* COM2 */
#define IRR0_LPT 0x20 /* centronics */
#define IRR0_GPIO 0x40 /* general purpose I/O */
#define IRR0_RTC 0x80 /* real-time clock */
/* IRR1 (error/clear) */
#define IRR1_DEBUG 0x01 /* debug switch */
#define IRR1_POWERFAIL 0x02 /* power fail */
#define IRR1_BUSERR 0x04 /* bus error */
#define IRR1_LPT_ACK 0x20 /* centronics interrupt ack. */
/* IRR2 (PCI) */
#define IRR2_FLOPPY_DMA 0x08 /* floppy DMA request */
#define IRR2_PCIIRQ0 0x10 /* PCIIRQ 0 */
#define IRR2_PCIIRQ1 0x20 /* PCIIRQ 1 */
#define IRR2_PCIIRQ2 0x40 /* PCIIRQ 2 */
#define IRR2_PCIIRQ3 0x80 /* PCIIRQ 3 */
/*
* The Algorithmics PMON initializes two DMA windows:
*
* PCI 8000.0000 -> Phys 0000.0000 (256MB)
*/
#define P4032_DMA_PCI_PCIBASE 0x80000000UL
#define P4032_DMA_PCI_PHYSBASE 0x00000000UL
#define P4032_DMA_PCI_SIZE (256 * 1024 * 1024)

View File

@ -0,0 +1,95 @@
/* $NetBSD: algor_p4032var.h,v 1.1 2001/06/01 16:00:03 thorpej Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/bus.h>
#include <dev/pci/pcivar.h>
struct p4032_config {
struct algor_bus_space ac_lociot;
struct algor_bus_space ac_iot;
struct algor_bus_space ac_memt;
struct algor_bus_dma_tag ac_pci_dmat;
struct algor_pci_chipset ac_pc;
struct extent *ac_io_ex;
struct extent *ac_mem_ex;
int ac_mallocsafe;
};
#ifdef _KERNEL
/*
* These are indexes into the interrupt mapping table for the
* on-board devices.
*/
#define P4032_IRQ_PCICTLR 0
#define P4032_IRQ_FLOPPY 1
#define P4032_IRQ_PCKBC 2
#define P4032_IRQ_COM1 3
#define P4032_IRQ_COM2 4
#define P4032_IRQ_LPT 5
#define P4032_IRQ_GPIO 6
#define P4032_IRQ_RTC 7
struct p4032_irqmap {
struct evcnt *irqcount;
int irqreg;
u_int8_t irqbit;
int xbarreg;
int xbarshift;
};
void algor_p4032_intr_disestablish(void *, void *);
void *algor_p4032_intr_establish(const struct p4032_irqmap *, int,
int (*)(void *), void *);
extern struct p4032_config p4032_configuration;
extern const struct p4032_irqmap p4032_8bit_irqmap[];
void algor_p4032loc_bus_io_init(bus_space_tag_t, void *);
void algor_p4032_bus_io_init(bus_space_tag_t, void *);
void algor_p4032_bus_mem_init(bus_space_tag_t, void *);
void algor_p4032_dma_init(struct p4032_config *);
void algor_p4032_intr_init(struct p4032_config *);
void algor_p4032_iointr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
#endif /* _KERNEL */

View File

@ -1,4 +1,4 @@
/* $NetBSD: led.c,v 1.1 2001/05/28 16:22:15 thorpej Exp $ */
/* $NetBSD: led.c,v 1.2 2001/06/01 16:00:03 thorpej Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -57,8 +57,8 @@
#endif
#if defined(ALGOR_P4032)
#define LEDBASE MIPS_PHYS_TO_KSEG1(XXX)
#define LED(x) XXX
#define LEDBASE MIPS_PHYS_TO_KSEG1(P4032_LED)
#define LED(x) ((3 - (x)) * 4)
#elif defined(ALGOR_P5064)
#define LEDBASE MIPS_PHYS_TO_KSEG1(P5064_LED1)
#define LED(x) ((3 - (x)) * 4)

View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.4 2001/05/31 07:24:23 nisimura Exp $ */
/* $NetBSD: machdep.c,v 1.5 2001/06/01 16:00:03 thorpej Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -224,18 +224,26 @@ mach_init(int argc, char *argv[], char *envp[])
strcpy(cpu_model, "Algorithmics P-4032");
vt->vt_addr = MIPS_PHYS_TO_KSEG1(XXX);
vt->vt_cfgbase = MIPS_PHYS_TO_KSEG1(XXX);
vt->vt_addr = MIPS_PHYS_TO_KSEG1(P4032_V962PBC);
vt->vt_cfgbase = MIPS_PHYS_TO_KSEG1(P4032_PCICFG);
vt->vt_adbase = 11;
led_display('v', '9', '6', '2');
vtpbc_init(&acp->ac_pc, vt);
algor_p4032loc_bus_mem_init(&acp->ac_locmemt, acp);
algor_p4032pci_bus_io_init(&acp->ac_iot, acp);
algor_p4032pci_bus_mem_init(&acp->ac_memt, acp);
led_display('l', 'i', 'o', ' ');
algor_p4032loc_bus_io_init(&acp->ac_lociot, acp);
led_display('i', 'o', ' ', ' ');
algor_p4032_bus_io_init(&acp->ac_iot, acp);
led_display('m', 'e', 'm', ' ');
algor_p4032_bus_mem_init(&acp->ac_memt, acp);
led_display('d', 'm', 'a', ' ');
algor_p4032_dma_init(acp);
led_display('i', 'n', 't', 'r');
algor_p4032_intr_init(acp);
#if NCOM > 0
/*
@ -243,8 +251,9 @@ mach_init(int argc, char *argv[], char *envp[])
* FIFO depth * character time.
* character time = (1000000 / (defaultrate / 10))
*/
led_display('c', 'o', 'n', 's');
DELAY(160000000 / comcnrate);
if (comcnattach(&acp->ac_locmemt, XXX, comcnrate,
if (comcnattach(&acp->ac_lociot, P4032_COM1, comcnrate,
COM_FREQ,
(TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) != 0)
panic("p4032: unable to initialize serial console");
@ -729,7 +738,10 @@ int
algor_get_ethaddr(struct pci_attach_args *pa, u_int8_t *buf)
{
#if defined(ALGOR_P5064)
#if defined(ALGOR_P4032)
if (pa->pa_bus != 0 || pa->pa_device != 5 || pa->pa_function != 0)
return (0);
#elif defined(ALGOR_P5064)
if (pa->pa_bus != 0 || pa->pa_device != 0 || pa->pa_function != 0)
return (0);
#endif

294
sys/arch/algor/conf/P4032 Normal file
View File

@ -0,0 +1,294 @@
# $NetBSD: P4032,v 1.1 2001/06/01 16:00:04 thorpej Exp $
#
# Algorithmics P-4032 kernel.
#
include "arch/algor/conf/std.algor"
#ident "P4032-$Revision: 1.1 $"
maxusers 32
# Platform Support
options ALGOR_P4032 # Algorithmics P-4032
#options ALGOR_P5064 # Algorithmics P-5064
#options ALGOR_P6032 # Algorithmics P-6032
options MIPS3_L2CACHE_ABSENT # No L2 cache on this machine
# Standard system options
options KTRACE # System call tracing support
options NTP # kernel PLL for NTP
# Diagnostic/debugging support options
options DIAGNOSTIC # Cheap kernel consistency checks
options DDB # kernel debugger
makeoptions DEBUG="-g"
#makeoptions DEBUGLIST="pattern1 pattern2 ..."
# File systems
file-system FFS # Fast file system
file-system MFS # Memory-based file system
file-system CD9660 # ISO-9660 CD-ROM FS (w/RockRidge extensions)
file-system MSDOSFS # MS-DOS-compatible file system
file-system NTFS # Windows/NT file system (experimental)
file-system NFS # Sun NFS-compatible file system client
file-system KERNFS # Kernel variable file system (/kern)
file-system PROCFS # Process file system (/proc)
# File system options
options NFSSERVER # Sun NFS-compatible file system server
#options FFS_EI # FFS Endian Independant support
options SOFTDEP # FFS soft updates support.
# Networking options
options INET # Internet protocol suite
options INET6 # IPV6
options IPSEC # IP security
options IPSEC_ESP # IP security (encryption part; define w/IPSEC)
#options IPSEC_DEBUG # debug for IP security
# 4.3BSD compatibility. Should be optional, but necessary for now.
options COMPAT_43
# Binary compatibility with previous versions of NetBSD.
#options COMPAT_09
options COMPAT_10
options COMPAT_11
options COMPAT_12
options COMPAT_13
options COMPAT_14
# System V-like message queues
options SYSVMSG
# System V-like semaphores
options SYSVSEM
# System V-like shared memory
options SYSVSHM
#options SHMMAXPGS=1024 # 1024 pages is the default
# Loadable Kernel Modules
options LKM
# Disable kernel security.
#options INSECURE
# Misc. options
#options PCI_NETBSD_CONFIGURE # NetBSD configures the PCI bus
options PCIVERBOSE # recognize "unknown" PCI devices
#options MIIVERBOSE # verbose PHY autoconfig messages
#options PCI_CONFIG_DUMP # verbosely dump PCI config space
options SCSIVERBOSE # Verbose SCSI errors
options UCONSOLE # users can use TIOCCONS (for xconsole)
#options PCMCIAVERBOSE
# The Alpha console firmware network boots using the BOOTP
# protocol, so we ask the NFS code to use BOOTP/DHCP as well,
# in case we have NFS root.
options NFS_BOOT_DHCP # superset of BOOTP
# WS console uses SUN or VT100 terminal emulation
#options WSEMUL_VT100
config netbsd root on ? type ?
#config netbsd root on sd0 type ffs
#config netbsd root on ? type nfs
mainbus0 at root
cpu* at mainbus0
# Devices on the P-4032 local I/O bus
mcclock* at mainbus? addr ?
com* at mainbus? addr ?
lpt* at mainbus? addr ?
#pckbc* at mainbus? addr ?
#fdc* at mainbus? addr ?
# PCI host bus adapter support
vtpbc* at mainbus?
# PCI bus support
pci* at vtpbc?
# PCI devices
#adv* at pci? dev ? function ? # AdvanSys SCSI
#adw* at pci? dev ? function ? # AdvanSys Wide SCSI
#options ADW_WDTR_DISABLE # disable WDTR
#options ADW_SDTR_DISABLE # disable SDTR
#options ADW_TAGQ_DISABLE # disable Tag Queuing
#ahc* at pci? dev ? function ? # Adaptec [23]94x, aic78x0 SCSI
#bha* at pci? dev ? function ? # BusLogic 9xx SCSI (untested)
#cac* at pci? dev ? function ? # Compaq array controller (untested)
#cy* at pci? dev ? function ? # Cyclades Cyclom-Y (untested)
#cz* at pci? dev ? function ? # Cyclades-Z (untested)
#de* at pci? dev ? function ? # 21x4x-based Ethernet
#dpt* at pci? dev ? function ? # DPT SmartCache/SmartRAID
#eap* at pci? dev ? function ? # Ensoniq AudioPCI
#en* at pci? dev ? function ? # ENI PCI ATM (untested)
#ep* at pci? dev ? function ? # 3COM 3c59x
#epic* at pci? dev ? function ? # SMC EPIC/100 Ethernet
#eso* at pci? dev ? function ? # ESS Solo-1 PCI AudioDrive
#ex* at pci? dev ? function ? # 3COM 3c90x[B] Ethernet
#fpa* at pci? dev ? function ? # DEC DEFPA FDDI
#fxp* at pci? dev ? function ? # Intel EEPRO 10+/100B
#gsip* at pci? dev ? function ? # NS DP83820 Gigabit Ethernet
#isp* at pci? dev ? function ? # Qlogic ISP 10x0 SCSI
#le* at pci? dev ? function ? # PCI LANCE Ethernet (untested)
#ncr* at pci? dev ? function ? # NCR 53c8xx SCSI
#pcib* at pci? dev ? function ? # Intel PCI-ISA Bridges
siop* at pci? dev ? function ? # Symbios 53c8xx SCSI
#mlx* at pci? dev ? function ? # Mylex DAC960 / DEC SWXCR (untested)
#ne* at pci? dev ? function ? # NE2000-compatible Ethernet
#ohci* at pci? dev ? function ? # USB Open Host Controller
#pciide* at pci? dev ? function ? # PCI IDE controllers
#pcscp* at pci? dev ? function ? # AMD Am53c974 PCscsi-PCI
ppb* at pci? dev ? function ? # PCI-PCI Bridges
#rtk* at pci? dev ? function ? # RealTek 8129/8139 Ethernet
#sip* at pci? dev ? function ? # SiS 900 Ethernet
#sv* at pci? dev ? function ? # S3 SonicVibes
#tga* at pci? dev ? function ? # DEC ZLXp-E[123] Graphics
#ti* at pci? dev ? function ? # Alteon Tigon Gig-E
#tl* at pci? dev ? function ? # TI ThunderLAN Ethernet
tlp* at pci? dev ? function ? # DECchip 21x4x and clones
options TLP_MATCH_21040
options TLP_MATCH_21041
options TLP_MATCH_21140
options TLP_MATCH_21142
#uhci* at pci? dev ? function ? # USB Univ. Host Controller
#vga* at pci? dev ? function ? # PCI VGA Graphics
#vr* at pci? dev ? function ? # VIA Rhine Fast Ethernet
#yds* at pci? dev ? function ? # Yamaha DS-1 PCI Audio
#audio* at eap?
#audio* at eso?
#audio* at sv?
#audio* at yds?
#opl* at eso?
#opl* at sv?
#opl* at yds?
#mpu* at eso?
#mpu* at yds?
# MII/PHY support
#exphy* at mii? phy ? # 3Com internal PHYs
#icsphy* at mii? phy ? # Integrated Circuit Systems ICS1890
#inphy* at mii? phy ? # Intel 82555 PHYs
#lxtphy* at mii? phy ? # Level One LXT-970 PHYs
#nsphy* at mii? phy ? # NS83840 PHYs
qsphy* at mii? phy ? # Quality Semiconductor QS6612 PHYs
#sqphy* at mii? phy ? # Seeq 80220/80221/80223 PHYs
#tlphy* at mii? phy ? # ThunderLAN PHYs
ukphy* at mii? phy ? # generic unknown PHYs
# SCSI bus support
#scsibus* at adv?
#scsibus* at adw?
#scsibus* at ahc?
#scsibus* at bha?
#scsibus* at dpt?
#scsibus* at isp?
scsibus* at siop?
#scsibus* at pcscp?
# SCSI devices
cd* at scsibus? target ? lun ? # SCSI CD-ROM drives
sd* at scsibus? target ? lun ? # SCSI disk drives
#st* at scsibus? target ? lun ? # SCSI tape drives
# ST506/ESDI/IDE devices
#wd* at pciide? channel ?
#wd* at wdc? drive ?
# ATAPI bus support
#atapibus* at pciide? channel ?
#atapibus* at wdc?
# ATAPI devices
#sd* at atapibus? drive ? # ATAPI disk devices
#cd* at atapibus? drive ? # ATAPI CD-ROM devices
# Floppy drives
#fd* at fdc? drive ?
# Hardware RAID devices
#ld* at cac? unit ?
#ld* at mlx? unit ?
# USB bus support
#usb* at uhci?
#usb* at ohci?
# USB Hubs
#uhub* at usb?
#uhub* at uhub? port ? configuration ? interface ?
# USB Mice
#ums* at uhub? port ? configuration ? interface ?
#wsmouse* at ums?
# USB Keyboards
#ukbd* at uhub? port ? configuration ? interface ?
#wskbd* at ukbd? console ?
# USB Generic HID devices
#uhid* at uhub? port ? configuration ? interface ?
# USB Printer
#ulpt* at uhub? port ? configuration ? interface ?
# USB Modem
#umodem* at uhub? port ? configuration ?
#ucom* at umodem?
# USB Mass Storage
#umass* at uhub? port ? configuration ? interface ?
#atapibus* at umass? channel ?
#scsibus* at umass? channel ?
# USB Ethernet adapters
#aue* at uhub? port ? # ADMtek AN986 Pegasus based adapters
#cue* at uhub? port ? # CATC USB-EL1201A based adapters
#kue* at uhub? port ? # Kawasaki LSI KL5KUSB101B based adapters
# Serial adapters
# FTDI FT8U100AX serial adapter
#uftdi* at uhub? port ?
#ucom* at uftdi? portno ?
# USB scanners
#uscanner* at uhub? port ?
# Y@P firmware loader
#uyap* at uhub? port ?
# USB Generic driver
#ugen* at uhub? port ?
# Workstation Console attachments
#wsdisplay* at vga?
#wskbd* at pckbd?
#wsmouse* at pms?
pseudo-device bpfilter 16
pseudo-device ccd 4
#pseudo-device raid 4 # RAIDframe disk driver
#options RAID_AUTOCONFIG # auto-configuration of RAID components
pseudo-device ipfilter 1
pseudo-device loop 1
pseudo-device md 1
pseudo-device ppp 4
pseudo-device pty # pseudo-terminals
pseudo-device sl 4
pseudo-device vnd 4
#pseudo-device gre 2 # generic L3 over IP tunnel
pseudo-device gif 4 # IPv[46] over IPv[46] tunnel (RFC1933)
#pseudo-device faith 1 # IPv[46] tcp relay translation i/f
#pseudo-device stf 1 # 6to4 IPv6 over IPv4 encapsulation
pseudo-device vlan # IEEE 802.1q encapsulation
pseudo-device sequencer 1 # MIDI sequencer
pseudo-device rnd # /dev/random and in-kernel generator
#options RND_COM # use "com" randomness too

View File

@ -1,4 +1,4 @@
# $NetBSD: files.algor,v 1.1 2001/05/28 16:22:16 thorpej Exp $
# $NetBSD: files.algor,v 1.2 2001/06/01 16:00:04 thorpej Exp $
# Algorithmics evaluation board specific configuration info.
@ -13,6 +13,12 @@ defopt ALGOR_P5064 # Algorithmics P-5064
defopt ALGOR_P6032 # Algorithmics P-6032
# Platform support files
file arch/algor/algor/algor_p4032_bus_io.c algor_p4032
file arch/algor/algor/algor_p4032_bus_locio.c algor_p4032
file arch/algor/algor/algor_p4032_bus_mem.c algor_p4032
file arch/algor/algor/algor_p4032_dma.c algor_p4032
file arch/algor/algor/algor_p4032_intr.c algor_p4032
file arch/algor/algor/algor_p5064_bus_io.c algor_p5064
file arch/algor/algor/algor_p5064_bus_mem.c algor_p5064
file arch/algor/algor/algor_p5064_dma.c algor_p5064
@ -110,7 +116,7 @@ file arch/algor/dev/vtpbc_mainbus.c vtpbc_mainbus
device pcib: isabus
attach pcib at pci
file arch/algor/pci/pcib.c pcib
file arch/algor/pci/pcib.c pcib & algor_p5064
file arch/algor/pci/pciide_machdep.c pciide
@ -139,3 +145,15 @@ major { fd = 0 }
# ISA Plug and Play devices
file arch/algor/isa/isapnp_machdep.c isapnp
#
# Devices on the P-4032 local I/O bus.
#
attach mcclock at mainbus with mcclock_mainbus
file arch/algor/dev/mcclock_mainbus.c mcclock_mainbus & algor_p4032
attach com at mainbus with com_mainbus
file arch/algor/dev/com_mainbus.c com_mainbus & algor_p4032
attach lpt at mainbus with lpt_mainbus
file arch/algor/dev/lpt_mainbus.c lpt_mainbus & algor_p4032

View File

@ -0,0 +1,146 @@
/* $NetBSD: com_mainbus.c,v 1.1 2001/06/01 16:00:04 thorpej Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "opt_algor_p4032.h"
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: com_mainbus.c,v 1.1 2001/06/01 16:00:04 thorpej Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/ioctl.h>
#include <sys/select.h>
#include <sys/tty.h>
#include <sys/proc.h>
#include <sys/user.h>
#include <sys/conf.h>
#include <sys/file.h>
#include <sys/uio.h>
#include <sys/kernel.h>
#include <sys/syslog.h>
#include <sys/types.h>
#include <sys/device.h>
#include <machine/autoconf.h>
#include <machine/intr.h>
#include <machine/bus.h>
#include <dev/ic/comreg.h>
#include <dev/ic/comvar.h>
#if defined(ALGOR_P4032)
#include <algor/algor/algor_p4032var.h>
#endif
struct com_mainbus_softc {
struct com_softc sc_com; /* real "com" softc */
/* mainbus-specific goo. */
void *sc_ih; /* interrupt handler */
};
int com_mainbus_match(struct device *, struct cfdata *, void *);
void com_mainbus_attach(struct device *, struct device *, void *);
void com_mainbus_cleanup(void *);
struct cfattach com_mainbus_ca = {
sizeof(struct com_mainbus_softc), com_mainbus_match,
com_mainbus_attach
};
int
com_mainbus_match(struct device *parent, struct cfdata *match, void *aux)
{
struct mainbus_attach_args *ma = aux;
/* Always present. */
if (strcmp(ma->ma_name, match->cf_driver->cd_name) == 0)
return (1);
return (0);
}
void
com_mainbus_attach(struct device *parent, struct device *self, void *aux)
{
struct com_mainbus_softc *msc = (void *)self;
struct com_softc *sc = &msc->sc_com;
struct mainbus_attach_args *ma = aux;
sc->sc_iot = ma->ma_st;
sc->sc_iobase = ma->ma_addr;
if (com_is_console(sc->sc_iot, sc->sc_iobase, &sc->sc_ioh) == 0 &&
bus_space_map(sc->sc_iot, sc->sc_iobase, COM_NPORTS, 0,
&sc->sc_ioh) != 0) {
printf(": can't map i/o space\n");
return;
}
sc->sc_frequency = COM_FREQ;
com_attach_subr(sc);
#if defined(ALGOR_P4032)
msc->sc_ih = algor_p4032_intr_establish(&p4032_8bit_irqmap[ma->ma_irq],
IPL_SERIAL, comintr, sc);
#endif
if (msc->sc_ih == NULL) {
printf("%s: unable to establish interrupt\n",
sc->sc_dev.dv_xname);
return;
}
/*
* Shutdown hook for buggy BIOSs that don't recognize the UART
* without a disabled FIFO.
*/
if (shutdownhook_establish(com_mainbus_cleanup, sc) == NULL)
panic("com_mainbus_attach: could not establish shutdown hook");
}
void
com_mainbus_cleanup(void *arg)
{
struct com_softc *sc = arg;
if (ISSET(sc->sc_hwflags, COM_HW_FIFO))
bus_space_write_1(sc->sc_iot, sc->sc_ioh, com_fifo, 0);
}

View File

@ -0,0 +1,125 @@
/* $NetBSD: lpt_mainbus.c,v 1.1 2001/06/01 16:00:04 thorpej Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: lpt_mainbus.c,v 1.1 2001/06/01 16:00:04 thorpej Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/ioctl.h>
#include <sys/select.h>
#include <sys/tty.h>
#include <sys/proc.h>
#include <sys/user.h>
#include <sys/conf.h>
#include <sys/file.h>
#include <sys/uio.h>
#include <sys/kernel.h>
#include <sys/syslog.h>
#include <sys/types.h>
#include <sys/device.h>
#include <machine/autoconf.h>
#include <machine/intr.h>
#include <machine/bus.h>
#include <dev/ic/lptreg.h>
#include <dev/ic/lptvar.h>
#if defined(ALGOR_P4032)
#include <algor/algor/algor_p4032var.h>
#endif
struct lpt_mainbus_softc {
struct lpt_softc sc_lpt; /* real "lpt" softc */
/* mainbus-specific goo. */
void *sc_ih; /* interrupt handler */
};
int lpt_mainbus_match(struct device *, struct cfdata *, void *);
void lpt_mainbus_attach(struct device *, struct device *, void *);
struct cfattach lpt_mainbus_ca = {
sizeof(struct lpt_mainbus_softc), lpt_mainbus_match,
lpt_mainbus_attach
};
int
lpt_mainbus_match(struct device *parent, struct cfdata *match, void *aux)
{
struct mainbus_attach_args *ma = aux;
/* Always present. */
if (strcmp(ma->ma_name, match->cf_driver->cd_name) == 0)
return (1);
return (0);
}
void
lpt_mainbus_attach(struct device *parent, struct device *self, void *aux)
{
struct lpt_mainbus_softc *msc = (void *)self;
struct lpt_softc *sc = &msc->sc_lpt;
struct mainbus_attach_args *ma = aux;
sc->sc_iot = ma->ma_st;
if (bus_space_map(sc->sc_iot, ma->ma_addr, LPT_NPORTS, 0,
&sc->sc_ioh) != 0) {
printf(": can't map i/o space\n");
return;
}
printf("\n");
lpt_attach_subr(sc);
#if defined(ALGOR_P4032)
sc->sc_ih = algor_p4032_intr_establish(&p4032_8bit_irqmap[ma->ma_irq],
IPL_TTY, lptintr, sc);
#endif
if (msc->sc_ih == NULL) {
printf("%s: unable to establish interrupt\n",
sc->sc_dev.dv_xname);
return;
}
}

View File

@ -1,4 +1,4 @@
/* $NetBSD: mainbus.c,v 1.1 2001/05/28 16:22:16 thorpej Exp $ */
/* $NetBSD: mainbus.c,v 1.2 2001/06/01 16:00:04 thorpej Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -72,15 +72,39 @@ int mainbus_submatch(struct device *, struct cfdata *, void *);
/* There can be only one. */
int mainbus_found;
struct mainbusdev {
const char *md_name;
bus_addr_t md_addr;
int md_irq;
};
#if defined(ALGOR_P4032)
#include <algor/algor/algor_p4032reg.h>
#include <algor/algor/algor_p4032var.h>
struct mainbusdev mainbusdevs[] = {
{ "cpu", -1, -1 },
{ "mcclock", P4032_RTC, P4032_IRQ_RTC },
{ "com", P4032_COM1, P4032_IRQ_COM1 },
{ "com", P4032_COM2, P4032_IRQ_COM2 },
{ "lpt", P4032_LPT, P4032_IRQ_LPT },
{ "pckbc", P4032_PCKBC, P4032_IRQ_PCKBC },
{ "fdc", P4032_FDC, P4032_IRQ_FLOPPY },
{ "vtpbc", P4032_V962PBC, -1 },
{ NULL, 0, 0 },
};
#endif /* ALGOR_P4032 */
#if defined(ALGOR_P5064)
#include <algor/algor/algor_p5064reg.h>
#include <algor/algor/algor_p5064var.h>
struct mainbus_attach_args mainbusdevs[] = {
{ "cpu", -1 },
{ "vtpbc", P5064_V360EPC },
struct mainbusdev mainbusdevs[] = {
{ "cpu", -1, -1 },
{ "vtpbc", P5064_V360EPC, -1 },
{ NULL, 0 },
{ NULL, 0, 0 },
};
#endif /* ALGOR_P5064 */
@ -97,7 +121,9 @@ mainbus_match(struct device *parent, struct cfdata *cf, void *aux)
void
mainbus_attach(struct device *parent, struct device *self, void *aux)
{
struct mainbus_attach_args *ma;
struct mainbus_attach_args ma;
struct mainbusdev *md;
bus_space_tag_t st;
#if defined(PCI_NETBSD_CONFIGURE)
struct extent *ioext, *memext;
pci_chipset_tag_t pc;
@ -108,7 +134,17 @@ mainbus_attach(struct device *parent, struct device *self, void *aux)
printf("\n");
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
#if defined(ALGOR_P5064)
#if defined(ALGOR_P4032)
/*
* Reserve the bottom 64K of the I/O space for ISA devices.
*/
ioext = extent_create("pciio", 0x00010000, 0x000effff,
M_DEVBUF, NULL, 0, EX_NOWAIT);
memext = extent_create("pcimem", 0x01000000, 0x07ffffff,
M_DEVBUF, NULL, 0, EX_NOWAIT);
pc = &p4032_configuration.ac_pc;
#elif defined(ALGOR_P5064)
/*
* Reserve the bottom 512K of the I/O space for ISA devices.
* According to the PMON sources, this is a work-around for
@ -120,16 +156,27 @@ mainbus_attach(struct device *parent, struct device *self, void *aux)
M_DEVBUF, NULL, 0, EX_NOWAIT);
pc = &p5064_configuration.ac_pc;
#endif /* ALGOR_P5064 */
#endif /* ALGOR_P4032 || ALGOR_P5064 */
pci_configure_bus(pc, ioext, memext, NULL);
extent_destroy(ioext);
extent_destroy(memext);
#endif /* NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) */
for (ma = mainbusdevs; ma->ma_name != NULL; ma++)
(void) config_found_sm(self, ma, mainbus_print,
#if defined(ALGOR_P4032)
st = &p4032_configuration.ac_lociot;
#elif defined(ALGOR_P5064)
st = NULL;
#endif
for (md = mainbusdevs; md->md_name != NULL; md++) {
ma.ma_name = md->md_name;
ma.ma_st = st;
ma.ma_addr = md->md_addr;
ma.ma_irq = md->md_irq;
(void) config_found_sm(self, &ma, mainbus_print,
mainbus_submatch);
}
}
int

View File

@ -0,0 +1,113 @@
/* $NetBSD: mcclock_mainbus.c,v 1.1 2001/06/01 16:00:04 thorpej Exp $ */
/*
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: mcclock_mainbus.c,v 1.1 2001/06/01 16:00:04 thorpej Exp $");
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <machine/autoconf.h>
#include <machine/bus.h>
#include <dev/ic/mc146818reg.h>
#include <algor/algor/clockvar.h>
#include <algor/dev/mcclockvar.h>
struct mcclock_mainbus_softc {
struct mcclock_softc sc_mcclock;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
};
int mcclock_mainbus_match(struct device *, struct cfdata *, void *);
void mcclock_mainbus_attach(struct device *, struct device *, void *);
struct cfattach mcclock_mainbus_ca = {
sizeof (struct mcclock_mainbus_softc), mcclock_mainbus_match,
mcclock_mainbus_attach,
};
void mcclock_mainbus_write(struct mcclock_softc *, u_int, u_int);
u_int mcclock_mainbus_read(struct mcclock_softc *, u_int);
const struct mcclock_busfns mcclock_mainbus_busfns = {
mcclock_mainbus_write, mcclock_mainbus_read,
};
int
mcclock_mainbus_match(struct device *parent, struct cfdata *match, void *aux)
{
struct mainbus_attach_args *ma = aux;
if (strcmp(ma->ma_name, match->cf_driver->cd_name) == 0)
return (1);
return (0);
}
void
mcclock_mainbus_attach(struct device *parent, struct device *self, void *aux)
{
struct mainbus_attach_args *ma = aux;
struct mcclock_mainbus_softc *sc = (void *)self;
sc->sc_iot = ma->ma_st;
if (bus_space_map(sc->sc_iot, ma->ma_addr, 2, 0, &sc->sc_ioh))
panic("mcclock_mainbus_attach: couldn't map clock I/O space");
mcclock_attach(&sc->sc_mcclock, &mcclock_mainbus_busfns);
}
void
mcclock_mainbus_write(struct mcclock_softc *mcsc, u_int reg, u_int datum)
{
struct mcclock_mainbus_softc *sc = (void *)mcsc;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
bus_space_write_1(iot, ioh, 0, reg);
bus_space_write_1(iot, ioh, 1, datum);
}
u_int
mcclock_mainbus_read(struct mcclock_softc *mcsc, u_int reg)
{
struct mcclock_mainbus_softc *sc = (void *)mcsc;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
bus_space_write_1(iot, ioh, 0, reg);
return bus_space_read_1(iot, ioh, 1);
}

View File

@ -1,4 +1,4 @@
/* $NetBSD: autoconf.h,v 1.1 2001/05/28 16:22:17 thorpej Exp $ */
/* $NetBSD: autoconf.h,v 1.2 2001/06/01 16:00:04 thorpej Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
@ -37,7 +37,9 @@
*/
struct mainbus_attach_args {
const char *ma_name; /* device name */
bus_space_tag_t ma_st; /* the space tag to use */
bus_addr_t ma_addr; /* system bus address */
int ma_irq; /* IRQ index */
};
#ifdef _KERNEL