2d7c87ebfb
ticks over at half the CPU clock speed, and set this flag for the known CPUs with this behaviour. Better names for this flag gratefully accepted! Also adjust comment about known R4000/R4400 revisions.
357 lines
10 KiB
C
357 lines
10 KiB
C
/* $NetBSD: cpu.h,v 1.62 2002/04/05 01:22:16 simonb Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)cpu.h 8.4 (Berkeley) 1/4/94
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*/
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#ifndef _CPU_H_
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#define _CPU_H_
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#include <mips/cpuregs.h>
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/*
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* Exported definitions unique to NetBSD/mips cpu support.
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*/
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#ifndef _LOCORE
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#include <sys/sched.h>
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#if defined(_KERNEL_OPT)
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#include "opt_lockdebug.h"
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#endif
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struct cpu_info {
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struct schedstate_percpu ci_schedstate; /* scheduler state */
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u_long ci_cpu_freq; /* CPU frequency */
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u_long ci_cycles_per_hz; /* CPU freq / hz */
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u_long ci_divisor_delay; /* for delay/DELAY */
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u_long ci_divisor_recip; /* scaled reciprocal of previous */
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#if defined(DIAGNOSTIC) || defined(LOCKDEBUG)
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u_long ci_spin_locks; /* # of spin locks held */
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u_long ci_simple_locks; /* # of simple locks held */
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#endif
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};
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#endif /* !defined(_LOCORE) */
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/*
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* CTL_MACHDEP definitions.
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*/
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#define CPU_CONSDEV 1 /* dev_t: console terminal device */
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#define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */
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#define CPU_ROOT_DEVICE 3 /* string: root device name */
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/*
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* Platform can override, but note this breaks userland compatibility
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* with other mips platforms.
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*/
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#ifndef CPU_MAXID
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#define CPU_MAXID 4 /* number of valid machdep ids */
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#define CTL_MACHDEP_NAMES { \
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{ 0, 0 }, \
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{ "console_device", CTLTYPE_STRUCT }, \
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{ "booted_kernel", CTLTYPE_STRING }, \
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{ "root_device", CTLTYPE_STRING }, \
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}
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#endif
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#ifdef _KERNEL
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#ifndef _LOCORE
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extern struct cpu_info cpu_info_store;
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#define curcpu() (&cpu_info_store)
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#define cpu_number() (0)
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#endif /* !_LOCORE */
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/*
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* Macros to find the CPU architecture we're on at run-time,
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* or if possible, at compile-time.
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*/
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#define CPU_ARCH_MIPSx 0 /* XXX unknown */
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#define CPU_ARCH_MIPS1 (1 << 0)
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#define CPU_ARCH_MIPS2 (1 << 1)
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#define CPU_ARCH_MIPS3 (1 << 2)
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#define CPU_ARCH_MIPS4 (1 << 3)
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#define CPU_ARCH_MIPS5 (1 << 4)
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#define CPU_ARCH_MIPS32 (1 << 5)
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#define CPU_ARCH_MIPS64 (1 << 6)
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#ifndef _LOCORE
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/* XXX simonb
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* Should the following be in a cpu_info type structure?
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* And how many of these are per-cpu vs. per-system? (Ie,
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* we can assume that all cpus have the same mmu-type, but
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* maybe not that all cpus run at the same clock speed.
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* Some SGI's apparently support R12k and R14k in the same
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* box.)
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*/
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extern int cpu_arch;
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extern int mips_cpu_flags;
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extern int mips_has_r4k_mmu;
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extern int mips_has_llsc;
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extern int mips3_pg_cached;
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#define CPU_MIPS_R4K_MMU 0x0001
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#define CPU_MIPS_NO_LLSC 0x0002
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#define CPU_MIPS_CAUSE_IV 0x0004
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#define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */
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#define CPU_MIPS_CACHED_CCA_MASK 0x0070
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#define CPU_MIPS_CACHED_CCA_SHIFT 4
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#define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */
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#define MIPS_NOT_SUPP 0x8000
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#ifdef _LKM
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/* Assume all CPU architectures are valid for LKM's */
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#define MIPS1 1
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#define MIPS3 1
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#define MIPS4 1
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#define MIPS32 1
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#define MIPS64 1
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#endif
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#if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0
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#error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified
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#endif
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#if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1
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#ifdef MIPS1
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# define CPUISMIPS3 0
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# define CPUIS64BITS 0
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# define CPUISMIPS32 0
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# define CPUISMIPS64 0
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# define CPUISMIPSNN 0
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# define MIPS_HAS_R4K_MMU 0
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# define MIPS_HAS_CLOCK 0
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# define MIPS_HAS_LLSC 0
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#endif /* MIPS1 */
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#if defined(MIPS3) || defined(MIPS4)
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# define CPUISMIPS3 1
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# define CPUIS64BITS 1
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# define CPUISMIPS32 0
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# define CPUISMIPS64 0
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# define CPUISMIPSNN 0
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# define MIPS_HAS_R4K_MMU 1
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# define MIPS_HAS_CLOCK 1
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# define MIPS_HAS_LLSC (mips_has_llsc)
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#endif /* MIPS3 || MIPS4 */
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#ifdef MIPS32
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# define CPUISMIPS3 1
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# define CPUIS64BITS 0
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# define CPUISMIPS32 1
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# define CPUISMIPS64 0
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# define CPUISMIPSNN 1
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# define MIPS_HAS_R4K_MMU 1
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# define MIPS_HAS_CLOCK 1
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# define MIPS_HAS_LLSC 1
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#endif /* MIPS32 */
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#ifdef MIPS64
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# define CPUISMIPS3 1
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# define CPUIS64BITS 1
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# define CPUISMIPS32 0
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# define CPUISMIPS64 1
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# define CPUISMIPSNN 1
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# define MIPS_HAS_R4K_MMU 1
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# define MIPS_HAS_CLOCK 1
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# define MIPS_HAS_LLSC 1
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#endif /* MIPS32 */
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#else /* run-time test */
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#define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu)
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#define MIPS_HAS_LLSC (mips_has_llsc)
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/* This test is ... rather bogus */
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#define CPUISMIPS3 ((cpu_arch & \
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(CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0)
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/* And these aren't much better while the previous test exists as is... */
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#define CPUISMIPS32 ((cpu_arch & CPU_ARCH_MIPS32) != 0)
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#define CPUISMIPS64 ((cpu_arch & CPU_ARCH_MIPS64) != 0)
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#define CPUISMIPSNN ((cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0)
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#define CPUIS64BITS ((cpu_arch & \
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(CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0)
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#define MIPS_HAS_CLOCK (cpu_arch >= CPU_ARCH_MIPS3)
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#endif /* run-time test */
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/* Shortcut for MIPS3 or above defined */
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#if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)
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#define MIPS3_PLUS 1
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#else
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#undef MIPS3_PLUS
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#endif
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/*
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* definitions of cpu-dependent requirements
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* referenced in generic code
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*/
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#define cpu_wait(p) /* nothing */
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#define cpu_swapout(p) panic("cpu_swapout: can't get here");
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void cpu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
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/*
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* Arguments to hardclock and gatherstats encapsulate the previous
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* machine state in an opaque clockframe.
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*/
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struct clockframe {
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int pc; /* program counter at time of interrupt */
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int sr; /* status register at time of interrupt */
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int ppl; /* previous priority level at time of interrupt */
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};
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/*
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* A port must provde CLKF_USERMODE() and CLKF_BASEPRI() for use
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* in machine-independent code. These differ on r4000 and r3000 systems;
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* provide them in the port-dependent file that includes this one, using
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* the macros below.
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*/
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/* mips1 versions */
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#define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV)
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#define MIPS1_CLKF_BASEPRI(framep) \
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((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_ENA_PREV)) == 0)
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/* mips3 versions */
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#define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER)
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#define MIPS3_CLKF_BASEPRI(framep) \
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((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_IE)) == 0)
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#ifdef IPL_ICU_MASK
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#define ICU_CLKF_BASEPRI(framep) ((framep)->ppl == 0)
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#endif
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#define CLKF_PC(framep) ((framep)->pc)
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#define CLKF_INTR(framep) (0)
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#if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */
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#define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep)
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#define CLKF_BASEPRI(framep) MIPS3_CLKF_BASEPRI(framep)
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#endif
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#if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */
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#define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep)
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#define CLKF_BASEPRI(framep) MIPS1_CLKF_BASEPRI(framep)
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#endif
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#ifdef IPL_ICU_MASK
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#undef CLKF_BASEPRI
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#define CLKF_BASEPRI(framep) ICU_CLKF_BASEPRI(framep)
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#endif
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#if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */
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#define CLKF_USERMODE(framep) \
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((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep))
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#define CLKF_BASEPRI(framep) \
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((CPUISMIPS3) ? MIPS3_CLKF_BASEPRI(framep): MIPS1_CLKF_BASEPRI(framep))
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#endif
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/*
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* This is used during profiling to integrate system time. It can safely
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* assume that the process is resident.
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*/
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#define PROC_PC(p) \
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(((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */
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/*
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* Preempt the current process if in interrupt from user mode,
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* or after the current trap/syscall if in system mode.
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*/
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#define need_resched(ci) \
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do { \
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want_resched = 1; \
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if (curproc != NULL) \
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aston(curproc); \
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} while (/*CONSTCOND*/0)
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/*
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* Give a profiling tick to the current process when the user profiling
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* buffer pages are invalid. On the MIPS, request an ast to send us
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* through trap, marking the proc as needing a profiling tick.
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*/
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#define need_proftick(p) \
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do { \
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(p)->p_flag |= P_OWEUPC; \
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aston(p); \
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} while (/*CONSTCOND*/0)
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/*
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* Notify the current process (p) that it has a signal pending,
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* process as soon as possible.
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*/
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#define signotify(p) aston(p)
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#define aston(p) ((p)->p_md.md_astpending = 1)
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extern int want_resched; /* resched() was called */
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/*
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* Misc prototypes and variable declarations.
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*/
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struct proc;
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struct user;
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extern struct proc *fpcurproc;
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/* trap.c */
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void netintr(void);
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int kdbpeek(vaddr_t);
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/* mips_machdep.c */
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void dumpsys(void);
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int savectx(struct user *);
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void mips_init_msgbuf(void);
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void savefpregs(struct proc *);
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void loadfpregs(struct proc *);
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/* locore*.S */
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int badaddr(void *, size_t);
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int badaddr64(uint64_t, size_t);
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/* mips_machdep.c */
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void cpu_identify(void);
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void mips_vector_init(void);
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#endif /* ! _LOCORE */
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#endif /* _KERNEL */
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#endif /* _CPU_H_ */
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