460f6b6383
Export i80321_local_dma_init(). Make !sc->sc_is_host configuration a little more friendly. Go back to using IABAR2 instead of IABAR3 for inbound SDRAM access.
181 lines
5.7 KiB
C
181 lines
5.7 KiB
C
/* $NetBSD: i80321var.h,v 1.7 2003/02/06 03:16:49 briggs Exp $ */
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/*
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* Copyright (c) 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_XSCALE_I80321VAR_H_
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#define _ARM_XSCALE_I80321VAR_H_
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#include <sys/queue.h>
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#include <dev/pci/pcivar.h>
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/*
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* There are roughly 32 interrupt sources.
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*/
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#define NIRQ 32
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struct intrhand {
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TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */
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int (*ih_func)(void *); /* handler */
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void *ih_arg; /* arg for handler */
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int ih_ipl; /* IPL_* */
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int ih_irq; /* IRQ number */
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};
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#define IRQNAMESIZE sizeof("iop321 irq 31")
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struct intrq {
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TAILQ_HEAD(, intrhand) iq_list; /* handler list */
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struct evcnt iq_ev; /* event counter */
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int iq_mask; /* IRQs to mask while handling */
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int iq_levels; /* IPL_*'s this IRQ has */
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int iq_ist; /* share type */
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};
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struct i80321_softc {
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struct device sc_dev; /* generic device glue */
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int sc_is_host; /* indicates if we're a host or
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plugged into another host */
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/*
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* This is the bus_space and handle used to access the
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* i80321 itself. This is filled in by the board-specific
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* front-end.
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*/
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bus_space_tag_t sc_st;
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bus_space_handle_t sc_sh;
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/* Handles for the various subregions. */
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bus_space_handle_t sc_atu_sh;
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bus_space_handle_t sc_mcu_sh;
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/*
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* We expect the board-specific front-end to have already mapped
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* the PCI I/O space .. it is only 64K, and I/O mappings tend to
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* be smaller than a page size, so it's generally more efficient
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* to map them all into virtual space in one fell swoop.
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*/
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vaddr_t sc_iow_vaddr; /* I/O window vaddr */
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/*
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* Variables that define the Inbound windows. The base address of
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* 0-2 are configured by a host via BARs. The xlate variable
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* defines the start of the local address space that it maps to.
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* The size variable defines the byte size.
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*
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* The first 3 windows are for incoming PCI memory read/write
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* cycles from a host. The 4th window, not configured by the
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* host (as it outside the normal BAR range) is the inbound
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* window for PCI devices controlled by the i80321.
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*/
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struct {
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uint32_t iwin_base_hi;
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uint32_t iwin_base_lo;
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uint32_t iwin_xlate;
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uint32_t iwin_size;
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} sc_iwin[4];
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/*
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* Variables that define the Outbound windows.
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*/
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struct {
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uint32_t owin_xlate_lo;
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uint32_t owin_xlate_hi;
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} sc_owin[2];
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/*
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* This is the PCI address that the Outbound I/O
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* window maps to.
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*/
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uint32_t sc_ioout_xlate;
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/* Bus space, DMA, and PCI tags for the PCI bus (private devices). */
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struct bus_space sc_pci_iot;
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struct bus_space sc_pci_memt;
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struct arm32_bus_dma_tag sc_pci_dmat;
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struct arm32_pci_chipset sc_pci_chipset;
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/* DMA window info for PCI DMA. */
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struct arm32_dma_range sc_pci_dma_range;
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/* GPIO state */
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uint8_t sc_gpio_dir; /* GPIO pin direction (1 == output) */
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uint8_t sc_gpio_val; /* GPIO output pin value */
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/* DMA tag for local devices. */
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struct arm32_bus_dma_tag sc_local_dmat;
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};
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/*
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* Arguments used to attach IOP built-ins.
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*/
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struct iopxs_attach_args {
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const char *ia_name; /* name of device */
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bus_space_tag_t ia_st; /* space tag */
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bus_space_handle_t ia_sh;/* handle of IOP base */
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bus_dma_tag_t ia_dmat; /* DMA tag */
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bus_addr_t ia_offset; /* offset of device from IOP base */
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bus_size_t ia_size; /* size of sub-device */
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};
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extern struct bus_space i80321_bs_tag;
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extern struct i80321_softc *i80321_softc;
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extern const char *i80321_irqnames[];
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extern void (*i80321_hardclock_hook)(void);
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void i80321_sdram_bounds(bus_space_tag_t, bus_space_handle_t,
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paddr_t *, psize_t *);
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void i80321_calibrate_delay(void);
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void i80321_icu_init(void);
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void i80321_intr_init(void);
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void *i80321_intr_establish(int, int, int (*)(void *), void *);
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void i80321_intr_disestablish(void *);
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void i80321_bs_init(bus_space_tag_t, void *);
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void i80321_io_bs_init(bus_space_tag_t, void *);
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void i80321_mem_bs_init(bus_space_tag_t, void *);
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void i80321_local_dma_init(struct i80321_softc *sc);
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void i80321_pci_init(pci_chipset_tag_t, void *);
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void i80321_attach(struct i80321_softc *);
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#endif /* _ARM_XSCALE_I80321VAR_H_ */
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