bsh 105db01dcd for Intel PXA2[15][05] processors, select write-back/write-through ... cache based on CPU id. write-through on PXA2[15]0 B2 stepping and earlier. write-back on C0 and C1 stepping (a.k.a PXA2[15]5 A0) options XSCALE_CACHE_WRITE_{THROUGH,BACK} can override it. for other XScale CPUs than PXA2xx, XSCALE_CACHE_WRITE_THROUGH works same as before.		2003-03-29 07:58:16 +00:00
..
arm	Add a couple of byte-wide variants that weren't implemented -- I guess because	2003-03-27 19:46:14 +00:00
arm32	for Intel PXA2[15][05] processors, select write-back/write-through	2003-03-29 07:58:16 +00:00
conf
footbridge	Add __KERNEL_RCSID tags to footbridge files.	2003-03-23 14:12:25 +00:00
fpe-arm
include	Garbage collect pmap_map, the last (and only?) use has been removed.	2003-03-23 15:59:23 +00:00
iomd
ixp12x0	Add __KERNEL_RCSID tags	2003-03-25 06:12:46 +00:00
mainbus
ofw
s3c2xx0
sa11x0	don't make kernels with options DEBUG print too much debug messages.	2003-03-23 08:59:02 +00:00
xscale	Bump copyright date for last.	2003-03-25 19:47:30 +00:00
Makefile