3f1ee498b5
The siisata driver supports the Silicon Image SteelVine family of SATA-II
controllers, interfacing the hardware with the ata(4) and atapi(4) sub-
systems.
The following controllers are supported by the siisata driver:
Silicon Image SiI3124 4-port PCI/PCI-X
Silicon Image SiI3132 2-port PCI-Express x1
Silicon Image SiI3531 1-port PCI-Express x1
SATA Native Command Queueing is not yet supported.
Device hot swapping is not yet supported.
Silicon Image's Software RAID is not yet supported by the
ataraid(4) driver.
Approved by: core (christos), releng (bouyer)
132 lines
5.0 KiB
C
132 lines
5.0 KiB
C
/* $NetBSD: siisatavar.h,v 1.1 2008/05/23 21:11:40 jnemeth Exp $ */
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/* Id: siisatavar.h,v 1.15 2008/05/22 13:48:54 jakllsch Exp */
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/* from ahcisatavar.h */
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/*
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* Copyright (c) 2006 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Manuel Bouyer.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*-
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* Copyright (c) 2007, 2008 Jonathan A. Kollasch.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef _IC_SIISATAVAR_H_
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#define _IC_SIISATAVAR_H_
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#include <dev/ic/siisatareg.h>
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#include <dev/ata/atavar.h>
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#define SIISATA_DEBUG
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#define DEBUG_INTR 0x01
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#define DEBUG_XFERS 0x02
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#define DEBUG_FUNCS 0x08
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#define DEBUG_PROBE 0x10
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#define DEBUG_DETACH 0x20
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#define DEBUG_DEBUG 0x80000000
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#ifdef SIISATA_DEBUG
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extern int siisata_debug_mask;
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#define SIISATA_DEBUG_PRINT(args, level) \
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if (siisata_debug_mask & (level)) \
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printf args
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#else
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#define SIISATA_DEBUG_PRINT(args, level)
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#endif
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struct siisata_softc {
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struct atac_softc sc_atac;
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bus_space_tag_t sc_grt;
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bus_space_handle_t sc_grh;
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bus_space_tag_t sc_prt;
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bus_space_handle_t sc_prh;
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bus_dma_tag_t sc_dmat;
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struct ata_channel *sc_chanarray[SIISATA_MAX_PORTS];
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struct siisata_channel {
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struct ata_channel ata_channel;
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bus_space_handle_t sch_scontrol;
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bus_space_handle_t sch_sstatus;
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bus_space_handle_t sch_serror;
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/* command activation PRBs */
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bus_dmamap_t sch_prbd;
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struct siisata_prb *sch_prb[SIISATA_MAX_SLOTS];
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bus_addr_t sch_bus_prb[SIISATA_MAX_SLOTS];
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bus_dmamap_t sch_datad[SIISATA_MAX_SLOTS];
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uint32_t sch_active_slots;
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} sc_channels[SIISATA_MAX_PORTS];
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int sc_have_dma64; /* 64-bit DMA available */
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int sc_chip; /* chip number */
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};
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#define SIISATANAME(sc) (device_xname((sc)->sc_atac.atac_dev))
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#define GRREAD(sc, reg) bus_space_read_4((sc)->sc_grt, (sc)->sc_grh, (reg))
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#define GRWRITE(sc, reg, val) bus_space_write_4((sc)->sc_grt, (sc)->sc_grh, (reg), (val))
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#define PRREAD(sc, reg) bus_space_read_4((sc)->sc_prt, (sc)->sc_prh, (reg))
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#define PRWRITE(sc, reg, val) bus_space_write_4((sc)->sc_prt, (sc)->sc_prh, (reg), (val))
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#define SIISATA_PRB_SYNC(sc, schp, slot, op) bus_dmamap_sync((sc)->sc_dmat, \
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(schp)->sch_prbd, slot * SIISATA_CMD_SIZE, SIISATA_CMD_SIZE, (op))
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#define SIISATA_NON_NCQ_SLOT 27
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void siisata_attach(struct siisata_softc *);
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int siisata_intr(void *);
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void siisata_resume(struct siisata_softc *);
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#endif /* !_IC_SIISATAVAR_H_ */
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