Import siisata(4) by Jonathan A. Kollasch.
The siisata driver supports the Silicon Image SteelVine family of SATA-II
controllers, interfacing the hardware with the ata(4) and atapi(4) sub-
systems.
The following controllers are supported by the siisata driver:
Silicon Image SiI3124 4-port PCI/PCI-X
Silicon Image SiI3132 2-port PCI-Express x1
Silicon Image SiI3531 1-port PCI-Express x1
SATA Native Command Queueing is not yet supported.
Device hot swapping is not yet supported.
Silicon Image's Software RAID is not yet supported by the
ataraid(4) driver.
Approved by: core (christos), releng (bouyer)
This commit is contained in:
jnemeth
parent
31d6cdf996
commit
3f1ee498b5
@ -1,4 +1,4 @@
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# $NetBSD: mi,v 1.1073 2008/05/23 00:20:37 lukem Exp $
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# $NetBSD: mi,v 1.1074 2008/05/23 21:11:40 jnemeth Exp $
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#
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# Note: don't delete entries from here - mark them as "obsolete" instead.
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#
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@ -1357,6 +1357,7 @@
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./usr/share/man/cat4/shb.0 man-sys-catman .cat
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./usr/share/man/cat4/shpcic.0 man-sys-catman .cat
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./usr/share/man/cat4/si.0 man-sys-catman .cat
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./usr/share/man/cat4/siisata.0 man-sys-catman .cat
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./usr/share/man/cat4/siop.0 man-sys-catman .cat
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./usr/share/man/cat4/sip.0 man-sys-catman .cat
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./usr/share/man/cat4/sisdrm.0 man-sys-catman .cat
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@ -3919,6 +3920,7 @@
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./usr/share/man/man4/shb.4 man-sys-man .man
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./usr/share/man/man4/shpcic.4 man-sys-man .man
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./usr/share/man/man4/si.4 man-sys-man .man
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./usr/share/man/man4/siisata.4 man-sys-man .man
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./usr/share/man/man4/siop.4 man-sys-man .man
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./usr/share/man/man4/sip.4 man-sys-man .man
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./usr/share/man/man4/sisdrm.4 man-sys-man .man
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@ -1,4 +1,4 @@
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# $NetBSD: Makefile,v 1.465 2008/05/18 22:05:59 cegger Exp $
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# $NetBSD: Makefile,v 1.466 2008/05/23 21:11:40 jnemeth Exp $
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# @(#)Makefile 8.1 (Berkeley) 6/18/93
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MAN= aac.4 ac97.4 acardide.4 aceride.4 acphy.4 acpidalb.4 \
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@ -42,7 +42,7 @@ MAN= aac.4 ac97.4 acardide.4 aceride.4 acphy.4 acpidalb.4 \
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rs5c372rtc.4 rtk.4 rtw.4 rum.4 \
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satalink.4 sbus.4 scc.4 scsi.4 sd.4 se.4 seeprom.4 sem.4 \
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ses.4 sf.4 sfb.4 sgsmix.4 shb.4 \
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shpcic.4 siop.4 sip.4 siside.4 sk.4 sl.4 slide.4 \
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shpcic.4 siisata.4 siop.4 sip.4 siside.4 sk.4 sl.4 slide.4 \
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sm.4 sn.4 sony.4 spc.4 speaker.4 spif.4 sqphy.4 ss.4 \
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st.4 ste.4 stge.4 sti.4 stpcide.4 sv.4 strip.4 \
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svwsata.4 swwdog.4 \
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76
share/man/man4/siisata.4
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76
share/man/man4/siisata.4
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@ -0,0 +1,76 @@
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.\" $NetBSD: siisata.4,v 1.1 2008/05/23 21:11:40 jnemeth Exp $
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.\"
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.\" Copyright (c) 2007, 2008 Jonathan A. Kollasch. All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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.\" INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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.\"
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.Dd May 21, 2008
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.Dt SIISATA 4
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.Os
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.Sh NAME
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.Nm siisata
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.Nd Silicon Image SATA-II controllers driver
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.Sh SYNOPSIS
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.Cd "siisata* at pci? dev ? function ?"
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.Sh DESCRIPTION
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The
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.Nm
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driver supports the Silicon Image SteelVine family of SATA-II controllers,
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interfacing the hardware with the
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.Xr ata 4
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and
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.Xr atapi 4
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subsystems.
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.Pp
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The following controllers are supported by the
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.Nm
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driver:
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.Pp
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.Bl -tag -width Ds -offset indent -compact
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.It Silicon Image SiI3124 4-port PCI/PCI-X
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.It Silicon Image SiI3132 2-port PCI-Express x1
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.It Silicon Image SiI3531 1-port PCI-Express x1
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.El
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.Sh SEE ALSO
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.Xr ata 4 ,
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.Xr atapi 4 ,
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.Xr pci 4 ,
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.Xr wd 4
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.Sh HISTORY
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The
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.Nm
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driver first appeared in
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.Nx 5.0 .
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.Sh AUTHORS
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The
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.Nm
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driver was written by
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.An Jonathan A. Kollasch Aq jakllsch@kollasch.net .
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.Sh BUGS
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.Bl -tag -width Ds -compact
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.It SATA Native Command Queueing is not yet supported .
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.It Device hot swapping is not yet supported .
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.It Silicon Image's Software RAID is not yet supported by the
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.Xr ataraid 4
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driver.
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.Xr raid 4
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can be used instead.
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.El
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1764
sys/dev/ic/siisata.c
Normal file
1764
sys/dev/ic/siisata.c
Normal file
File diff suppressed because it is too large
Load Diff
248
sys/dev/ic/siisatareg.h
Normal file
248
sys/dev/ic/siisatareg.h
Normal file
@ -0,0 +1,248 @@
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/* $NetBSD: siisatareg.h,v 1.1 2008/05/23 21:11:40 jnemeth Exp $ */
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/* Id: siisatareg.h,v 1.10 2008/05/21 15:51:36 jakllsch Exp */
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/*-
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* Copyright (c) 2007, 2008 Jonathan A. Kollasch.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/* Silicon Image SATA 2 controller register defines */
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#include <sys/cdefs.h>
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/* the SiI3124 has 4 ports, all others so far have less */
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#define SIISATA_MAX_PORTS 4
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/* the so far all parts have a full complement of slots */
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#define SIISATA_MAX_SLOTS 31
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/* structures */
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/* Scatter/Gather Entry */
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struct siisata_sge {
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#if 0
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uint32_t sge_dal; /* data address low */
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uint32_t sge_dah; /* " " high */
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#else
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uint64_t sge_da;
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#endif
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uint32_t sge_dc; /* data count (bytes) */
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uint32_t sge_flags; /* */
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#define SGE_FLAG_TRM __BIT(31)
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#define SGE_FLAG_LNK __BIT(30)
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#define SGE_FLAG_DRD __BIT(29)
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#define SGE_FLAG_XCF __BIT(28)
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} __attribute__((__packed__));
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/* Scatter/Gather Table */
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/* must be aligned to 64-bit boundary */
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struct siisata_sgt {
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struct siisata_sge sgt_sge[4];
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} __attribute__((__packed__));
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/* Port Request Block */
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struct siisata_prb {
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uint16_t prb_control; /* Control Field */
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#define PRB_CF_PROTOCOL_OVERRIDE __BIT(0)
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#define PRB_CF_RETRANSMIT __BIT(1)
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#define PRB_CF_EXTERNAL_COMMAND __BIT(2)
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#define PRB_CF_RECEIVE __BIT(3)
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#define PRB_CF_PACKET_READ __BIT(4)
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#define PRB_CF_PACKET_WRITE __BIT(5)
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#define PRB_CF_INTERRUPT_MASK __BIT(6)
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#define PRB_CF_SOFT_RESET __BIT(7)
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uint16_t prb_protocol_override;
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#define PRB_PO_PACKET __BIT(0)
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#define PRB_PO_LCQ __BIT(1)
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#define PRB_PO_NCQ __BIT(2)
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#define PRB_PO_READ __BIT(3)
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#define PRB_PO_WRITE __BIT(4)
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#define PRB_PO_TRANSPARENT __BIT(5)
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uint32_t prb_transfer_count;
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uint8_t prb_fis[20];
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uint32_t prb_reserved_0x1C; /* "must be zero" */
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/* First SGE in PRB is always reserved for ATAPI in this implementation. */
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uint8_t prb_atapi[16]; /* zero for non-ATAPI */
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struct siisata_sge prb_sge[1]; /* extended to NSGE */
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} __attribute__((__packed__));
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#define SIISATA_NSGE ((MAXPHYS/PAGE_SIZE) + 1)
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#define SIISATA_CMD_ALIGN 0x7f
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#define SIISATA_CMD_SIZE \
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( ( sizeof(struct siisata_prb) + (SIISATA_NSGE - 1) * sizeof(struct siisata_sge) + SIISATA_CMD_ALIGN ) & ~SIISATA_CMD_ALIGN )
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/* PCI stuff */
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#define SIISATA_PCI_BAR0 0x10
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#define SIISATA_PCI_BAR1 0x18
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#define SIISATA_PCI_BAR2 0x20
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/* BAR 0 */
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/* port n slot status */
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#define GR_PXSS(n) (n*4)
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/* global control */
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#define GR_GC 0x40
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/* global interrupt status */
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#define GR_GIS 0x44
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/* phy config - don't touch */
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#define GR_PHYC 0x48
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/* BIST */
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#define GR_BIST_CONTROL 0x50
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#define GR_BIST_PATTERN 0x54
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#define GR_BIST_STATUS 0x58
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/* I2C SiI3132 */
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#define GR_SII3132_IICCONTROL 0x60
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#define GR_SII3132_IICSTATUS 0x64
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#define GR_SII3132_IICSLAVEADDR 0x68
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#define GR_SII3132_IICDATA 0x6c
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/* Flash */
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#define GR_FLSHADDR 0x70
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#define GR_FLSHDATA 0x74
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/* I2C SiI3124 */
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#define GR_SII3124_IICADDR 0x78
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#define GR_SII3124_IICDATA 0x7c
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/* GR_GC bits */
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#define GR_GC_GLBLRST __BIT(31)
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#define GR_GC_MSIACK __BIT(30)
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#define GR_GC_I2CINTEN __BIT(29)
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#define GR_GC_PERRRPTDSBL __BIT(28)
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#define GR_GC_3GBPS __BIT(24)
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#define GR_GC_REQ64 __BIT(20)
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#define GR_GC_DEVSEL __BIT(19)
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#define GR_GC_STOP __BIT(18)
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#define GR_GC_TRDY __BIT(17)
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#define GR_GC_M66EN __BIT(16)
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#define GR_GC_PXIE_MASK __BITS(SIISATA_MAX_PORTS - 1, 0)
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#define GR_GC_PXIE(n) __SHIFTIN(__BIT(n), GR_GC_PXIE_MASK)
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/* GR_GIS bits */
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#define GR_GIS_I2C __BIT(29)
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#define GR_GIS_PXIS_MASK __BITS(SIISATA_MAX_PORTS - 1, 0)
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#define GR_GIS_PXIS(n) __SHIFTIN(__BIT(n), GR_GIS_PXIS_MASK)
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/* BAR 1 */
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/* hmm, this could use a better name */
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#define PR_PORT_SIZE 0x2000
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#define PR_SLOT_SIZE 0x80
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/* get the register by port number and offset */
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#define PRO(p) (PR_PORT_SIZE * p)
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#define PRX(p,r) (PRO(p) + r)
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#define PRSX(p,s,o) (PRX(p, PR_SLOT_SIZE * s + o))
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#define PRSO_RTC 0x04 /* recieved transfer count */
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#define PRSO_FIS 0x08 /* base of FIS */
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#define PRO_PCS 0x1000 /* (write) port control set */
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#define PRO_PS PRO_PCS /* (read) port status */
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#define PRO_PCC 0x1004 /* port control clear */
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#define PRO_PIS 0x1008 /* port interrupt status */
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#define PRO_PIES 0x1010 /* port interrupt enable set */
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#define PRO_PIEC 0x1014 /* port interrupt enable clear */
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#define PRO_32BAUA 0x101c /* 32-bit activation upper address */
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#define PRO_PCEF 0x1020 /* port command execution fifo */
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#define PRO_PCE 0x1024 /* port command error */
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#define PRO_PFISC 0x1028 /* port FIS config */
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#define PRO_PCIRFIFOT 0x102c /* pci request fifo threshhold */
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#define PRO_P8B10BDEC 0x1040 /* port 8B/10B decode error counter */
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#define PRO_PCRCEC 0x1044 /* port crc error count */
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#define PRO_PHEC 0x1048 /* port handshake error count */
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#define PRO_PPHYC 0x1050 /* phy config */
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#define PRO_PSS 0x1800 /* port slot status */
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/* technically this is a shadow of the CAR */
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#define PRO_CAR 0x1c00
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#define PRO_CARX(p,s) (PRX(p, PRO_CAR) + s * sizeof(uint64_t))
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#define PRO_PCR 0x1e04 /* port context register */
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#define PRO_SCONTROL 0x1f00 /* SControl */
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#define PRO_SSTATUS 0x1f04 /* SStatus */
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#define PRO_SERROR 0x1f08 /* SError */
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#define PRO_SACTIVE 0x1f0c /* SActive */
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/* Port Command Error */
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#define PR_PCE_DEVICEERROR 1
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#define PR_PCE_SDBERROR 2
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#define PR_PCE_DATAFISERROR 3
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#define PR_PCE_SENDFISERROR 4
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#define PR_PCE_INCONSISTENTSTATE 5
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#define PR_PCE_DIRECTIONERROR 6
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#define PR_PCE_UNDERRUNERROR 7
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#define PR_PCE_OVERRUNERROR 8
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#define PR_PCE_LINKFIFOOVERRUN 9
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#define PR_PCE_PACKETPROTOCOLERROR 11
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#define PR_PCE_PLDSGTERRORBOUNDARY 16
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#define PR_PCE_PLDSGTERRORTARGETABORT 17
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#define PR_PCE_PLDSGTERRORMASTERABORT 18
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#define PR_PCE_PLDSGTERRORPCIPERR 19
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#define PR_PCE_PLDCMDERRORBOUNDARY 24
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#define PR_PCE_PLDCMDERRORTARGETABORT 25
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#define PR_PCE_PLDCMDERRORMASTERABORT 26
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#define PR_PCE_PLDCMDERRORPCIPERR 27
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#define PR_PCE_PSDERRORTARGETABORT 33
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#define PR_PCE_PSDERRORMASTERABORT 34
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#define PR_PCE_PSDERRORPCIPERR 35
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#define PR_PCE_SENDSERVICEERROROR 36
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#define PR_PIS_UNMASKED_SHIFT 16
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#define PR_PIS_CMDCMPL __BIT(0) /* command completion */
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#define PR_PIS_CMDERRR __BIT(1) /* command error */
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#define PR_PIS_PRTRDY __BIT(2) /* port ready */
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#define PR_PIS_PMCHNG __BIT(3) /* power management state change */
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#define PR_PIS_PHYRDYCHG __BIT(4)
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#define PR_PIS_COMWAKE __BIT(5)
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#define PR_PIS_UNRECFIS __BIT(6)
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#define PR_PIS_DEVEXCHG __BIT(7)
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#define PR_PIS_8B10BDET __BIT(8)
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#define PR_PIS_CRCET __BIT(9)
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#define PR_PIS_HET __BIT(10)
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#define PR_PIS_SDBN __BIT(11)
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#define PR_PC_PORT_RESET __BIT(0)
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#define PR_PC_DEVICE_RESET __BIT(1)
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#define PR_PC_PORT_INITIALIZE __BIT(2)
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#define PR_PC_INCOR __BIT(3)
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#define PR_PC_LED_DISABLE __BIT(4)
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#define PR_PC_PACKET_LENGTH __BIT(5)
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#define PR_PC_RESUME __BIT(6)
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#define PR_PC_TXBIST __BIT(7)
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#define PR_PC_CONT_DISABLE __BIT(8)
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#define PR_PC_SCRAMBLER_DISABLE __BIT(9)
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#define PR_PC_32BA __BIT(10)
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#define PR_PC_INTERLOCK_REJECT __BIT(11)
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#define PR_PC_INTERLOCK_ACCEPT __BIT(12)
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#define PR_PC_PMP_ENABLE __BIT(13)
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#define PR_PC_AIA __BIT(14)
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#define PR_PC_LED_ON __BIT(15)
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#define PR_PC_OOB_BYPASS __BIT(25)
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#define PR_PS_PORT_READY __BIT(31)
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#define PR_PSS_ATTENTION __BIT(31)
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#define PR_PSS_SLOT_MASK __BITS(30, 0)
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#define PR_PXSS(n) __SHIFTIN(__BIT(n), PR_PSS_SLOT_MASK)
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131
sys/dev/ic/siisatavar.h
Normal file
131
sys/dev/ic/siisatavar.h
Normal file
@ -0,0 +1,131 @@
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/* $NetBSD: siisatavar.h,v 1.1 2008/05/23 21:11:40 jnemeth Exp $ */
|
||||
/* Id: siisatavar.h,v 1.15 2008/05/22 13:48:54 jakllsch Exp */
|
||||
|
||||
/* from ahcisatavar.h */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2006 Manuel Bouyer.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Manuel Bouyer.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2007, 2008 Jonathan A. Kollasch.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _IC_SIISATAVAR_H_
|
||||
#define _IC_SIISATAVAR_H_
|
||||
|
||||
#include <dev/ic/siisatareg.h>
|
||||
#include <dev/ata/atavar.h>
|
||||
|
||||
#define SIISATA_DEBUG
|
||||
|
||||
#define DEBUG_INTR 0x01
|
||||
#define DEBUG_XFERS 0x02
|
||||
#define DEBUG_FUNCS 0x08
|
||||
#define DEBUG_PROBE 0x10
|
||||
#define DEBUG_DETACH 0x20
|
||||
#define DEBUG_DEBUG 0x80000000
|
||||
#ifdef SIISATA_DEBUG
|
||||
extern int siisata_debug_mask;
|
||||
#define SIISATA_DEBUG_PRINT(args, level) \
|
||||
if (siisata_debug_mask & (level)) \
|
||||
printf args
|
||||
#else
|
||||
#define SIISATA_DEBUG_PRINT(args, level)
|
||||
#endif
|
||||
|
||||
struct siisata_softc {
|
||||
struct atac_softc sc_atac;
|
||||
bus_space_tag_t sc_grt;
|
||||
bus_space_handle_t sc_grh;
|
||||
bus_space_tag_t sc_prt;
|
||||
bus_space_handle_t sc_prh;
|
||||
bus_dma_tag_t sc_dmat;
|
||||
|
||||
struct ata_channel *sc_chanarray[SIISATA_MAX_PORTS];
|
||||
struct siisata_channel {
|
||||
struct ata_channel ata_channel;
|
||||
bus_space_handle_t sch_scontrol;
|
||||
bus_space_handle_t sch_sstatus;
|
||||
bus_space_handle_t sch_serror;
|
||||
|
||||
/* command activation PRBs */
|
||||
bus_dmamap_t sch_prbd;
|
||||
struct siisata_prb *sch_prb[SIISATA_MAX_SLOTS];
|
||||
bus_addr_t sch_bus_prb[SIISATA_MAX_SLOTS];
|
||||
|
||||
bus_dmamap_t sch_datad[SIISATA_MAX_SLOTS];
|
||||
|
||||
uint32_t sch_active_slots;
|
||||
} sc_channels[SIISATA_MAX_PORTS];
|
||||
|
||||
int sc_have_dma64; /* 64-bit DMA available */
|
||||
int sc_chip; /* chip number */
|
||||
};
|
||||
|
||||
#define SIISATANAME(sc) (device_xname((sc)->sc_atac.atac_dev))
|
||||
|
||||
#define GRREAD(sc, reg) bus_space_read_4((sc)->sc_grt, (sc)->sc_grh, (reg))
|
||||
#define GRWRITE(sc, reg, val) bus_space_write_4((sc)->sc_grt, (sc)->sc_grh, (reg), (val))
|
||||
#define PRREAD(sc, reg) bus_space_read_4((sc)->sc_prt, (sc)->sc_prh, (reg))
|
||||
#define PRWRITE(sc, reg, val) bus_space_write_4((sc)->sc_prt, (sc)->sc_prh, (reg), (val))
|
||||
|
||||
#define SIISATA_PRB_SYNC(sc, schp, slot, op) bus_dmamap_sync((sc)->sc_dmat, \
|
||||
(schp)->sch_prbd, slot * SIISATA_CMD_SIZE, SIISATA_CMD_SIZE, (op))
|
||||
|
||||
#define SIISATA_NON_NCQ_SLOT 27
|
||||
|
||||
void siisata_attach(struct siisata_softc *);
|
||||
int siisata_intr(void *);
|
||||
|
||||
void siisata_resume(struct siisata_softc *);
|
||||
|
||||
#endif /* !_IC_SIISATAVAR_H_ */
|
||||
@ -1,4 +1,4 @@
|
||||
# $NetBSD: files.pci,v 1.303 2008/03/29 00:16:26 cube Exp $
|
||||
# $NetBSD: files.pci,v 1.304 2008/05/23 21:11:40 jnemeth Exp $
|
||||
#
|
||||
# Config file and device description for machine-independent PCI code.
|
||||
# Included by ports that need it. Requires that the SCSI files be
|
||||
@ -931,3 +931,10 @@ defflag opt_r128fb.h R128FB_WAIT
|
||||
device lii: ether, ifnet, arp, mii
|
||||
attach lii at pci
|
||||
file dev/pci/if_lii.c lii
|
||||
|
||||
# Silicon Image SteelVine SATA-II controllers
|
||||
define siisata
|
||||
file dev/ic/siisata.c atapibus & atabus & siisata
|
||||
device siisata: ata, ata_dma, ata_udma, sata, siisata
|
||||
attach siisata at pci with siisata_pci
|
||||
file dev/pci/siisata_pci.c siisata_pci
|
||||
|
||||
307
sys/dev/pci/siisata_pci.c
Normal file
307
sys/dev/pci/siisata_pci.c
Normal file
@ -0,0 +1,307 @@
|
||||
/* $NetBSD: siisata_pci.c,v 1.1 2008/05/23 21:11:40 jnemeth Exp $ */
|
||||
/* Id: siisata_pci.c,v 1.11 2008/05/21 16:20:11 jakllsch Exp */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2006 Manuel Bouyer.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Manuel Bouyer.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2007, 2008 Jonathan A. Kollasch.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/param.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/systm.h>
|
||||
|
||||
#include <uvm/uvm_extern.h>
|
||||
|
||||
#include <dev/pci/pcivar.h>
|
||||
#include <dev/pci/pcidevs.h>
|
||||
#include <dev/ic/siisatavar.h>
|
||||
|
||||
struct siisata_pci_softc {
|
||||
struct siisata_softc si_sc;
|
||||
pci_chipset_tag_t sc_pc;
|
||||
pcitag_t sc_pcitag;
|
||||
};
|
||||
|
||||
static int siisata_pci_match(device_t, cfdata_t, void *);
|
||||
static void siisata_pci_attach(device_t, device_t, void *);
|
||||
static bool siisata_pci_resume(device_t PMF_FN_PROTO);
|
||||
|
||||
static const struct siisata_pci_product {
|
||||
pci_vendor_id_t spp_vendor;
|
||||
pci_product_id_t spp_product;
|
||||
int spp_ports;
|
||||
int spp_chip;
|
||||
|
||||
} siisata_pci_products[] = {
|
||||
{
|
||||
PCI_VENDOR_CMDTECH, PCI_PRODUCT_CMDTECH_3124,
|
||||
4, 3124
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_CMDTECH, PCI_PRODUCT_CMDTECH_3132,
|
||||
2, 3132
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_CMDTECH, PCI_PRODUCT_CMDTECH_3531,
|
||||
1, 3531
|
||||
},
|
||||
{
|
||||
0, 0,
|
||||
0, 0
|
||||
},
|
||||
};
|
||||
|
||||
CFATTACH_DECL_NEW(siisata_pci, sizeof(struct siisata_pci_softc),
|
||||
siisata_pci_match, siisata_pci_attach, NULL, NULL);
|
||||
|
||||
static const struct siisata_pci_product *
|
||||
siisata_pci_lookup(const struct pci_attach_args * pa)
|
||||
{
|
||||
const struct siisata_pci_product *spp;
|
||||
|
||||
for (spp = siisata_pci_products; spp->spp_ports > 0; spp++) {
|
||||
if (PCI_VENDOR(pa->pa_id) == spp->spp_vendor &&
|
||||
PCI_PRODUCT(pa->pa_id) == spp->spp_product)
|
||||
return spp;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int
|
||||
siisata_pci_match(device_t parent, cfdata_t match, void *aux)
|
||||
{
|
||||
struct pci_attach_args *pa = aux;
|
||||
|
||||
if (siisata_pci_lookup(pa) != NULL)
|
||||
return 3;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool
|
||||
siisata_pci_resume(device_t dv PMF_FN_ARGS)
|
||||
{
|
||||
struct siisata_pci_softc *psc = device_private(dv);
|
||||
struct siisata_softc *sc = &psc->si_sc;
|
||||
int s;
|
||||
|
||||
s = splbio();
|
||||
siisata_resume(sc);
|
||||
splx(s);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void
|
||||
siisata_pci_attach(device_t parent, device_t self, void *aux)
|
||||
{
|
||||
struct pci_attach_args *pa = aux;
|
||||
struct siisata_pci_softc *psc = device_private(self);
|
||||
struct siisata_softc *sc = &psc->si_sc;
|
||||
char devinfo[256];
|
||||
const char *intrstr;
|
||||
pci_intr_handle_t intrhandle;
|
||||
pcireg_t csr, memtype;
|
||||
const struct siisata_pci_product *spp;
|
||||
void *ih;
|
||||
bus_space_tag_t memt;
|
||||
bus_space_handle_t memh;
|
||||
uint32_t gcreg;
|
||||
int memh_valid;
|
||||
bus_size_t grsize, prsize;
|
||||
|
||||
sc->sc_atac.atac_dev = self;
|
||||
|
||||
psc->sc_pc = pa->pa_pc;
|
||||
psc->sc_pcitag = pa->pa_tag;
|
||||
|
||||
pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo));
|
||||
aprint_naive(": SATA-II HBA\n");
|
||||
aprint_normal(": %s\n", devinfo);
|
||||
|
||||
/* map bar0 */
|
||||
#if 1
|
||||
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIISATA_PCI_BAR0);
|
||||
#else
|
||||
memtype = PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT;
|
||||
#endif
|
||||
switch (memtype) {
|
||||
case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
|
||||
case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
|
||||
memh_valid = (pci_mapreg_map(pa, SIISATA_PCI_BAR0,
|
||||
memtype, 0, &memt, &memh, NULL, &grsize) == 0);
|
||||
break;
|
||||
default:
|
||||
memh_valid = 0;
|
||||
}
|
||||
if (memh_valid) {
|
||||
sc->sc_grt = memt;
|
||||
sc->sc_grh = memh;
|
||||
} else {
|
||||
aprint_error("%s: unable to map device global registers\n",
|
||||
SIISATANAME(sc));
|
||||
return;
|
||||
}
|
||||
|
||||
/* map bar1 */
|
||||
#if 1
|
||||
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIISATA_PCI_BAR1);
|
||||
#else
|
||||
memtype = PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT;
|
||||
#endif
|
||||
switch (memtype) {
|
||||
case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
|
||||
case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
|
||||
memh_valid = (pci_mapreg_map(pa, SIISATA_PCI_BAR1,
|
||||
memtype, 0, &memt, &memh, NULL, &prsize) == 0);
|
||||
break;
|
||||
default:
|
||||
memh_valid = 0;
|
||||
}
|
||||
if (memh_valid) {
|
||||
sc->sc_prt = memt;
|
||||
sc->sc_prh = memh;
|
||||
} else {
|
||||
bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize);
|
||||
aprint_error("%s: unable to map device port registers\n",
|
||||
SIISATANAME(sc));
|
||||
return;
|
||||
}
|
||||
|
||||
if (pci_dma64_available(pa)) {
|
||||
sc->sc_dmat = pa->pa_dmat64;
|
||||
sc->sc_have_dma64 = 1;
|
||||
aprint_debug("64-bit PCI DMA available\n");
|
||||
} else {
|
||||
sc->sc_dmat = pa->pa_dmat;
|
||||
sc->sc_have_dma64 = 0;
|
||||
}
|
||||
|
||||
/* map interrupt */
|
||||
if (pci_intr_map(pa, &intrhandle) != 0) {
|
||||
bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize);
|
||||
bus_space_unmap(sc->sc_prt, sc->sc_prh, prsize);
|
||||
aprint_error("%s: couldn't map interrupt\n", SIISATANAME(sc));
|
||||
return;
|
||||
}
|
||||
intrstr = pci_intr_string(pa->pa_pc, intrhandle);
|
||||
ih = pci_intr_establish(pa->pa_pc, intrhandle,
|
||||
IPL_BIO, siisata_intr, sc);
|
||||
if (ih == NULL) {
|
||||
bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize);
|
||||
bus_space_unmap(sc->sc_prt, sc->sc_prh, prsize);
|
||||
aprint_error("%s: couldn't establish interrupt"
|
||||
"at %s\n", SIISATANAME(sc), intrstr);
|
||||
return;
|
||||
}
|
||||
aprint_normal("%s: interrupting at %s\n", SIISATANAME(sc),
|
||||
intrstr ? intrstr : "unknown interrupt");
|
||||
|
||||
/* fill in number of ports on this device */
|
||||
spp = siisata_pci_lookup(pa);
|
||||
if (spp != NULL) {
|
||||
sc->sc_atac.atac_nchannels = spp->spp_ports;
|
||||
sc->sc_chip = spp->spp_chip;
|
||||
} else
|
||||
/* _match() should prevent us from getting here */
|
||||
panic("siisata: the universe might be falling apart!\n");
|
||||
|
||||
gcreg = GRREAD(sc, GR_GC);
|
||||
|
||||
aprint_normal("%s: SiI%d on ", SIISATANAME(sc), sc->sc_chip);
|
||||
if (sc->sc_chip == 3124) {
|
||||
aprint_normal("%d-bit, ", (gcreg & GR_GC_REQ64) ? 64 : 32);
|
||||
switch (gcreg & (GR_GC_DEVSEL | GR_GC_STOP | GR_GC_TRDY)) {
|
||||
case 0:
|
||||
aprint_normal("%d", (gcreg & GR_GC_M66EN) ? 66 : 33);
|
||||
break;
|
||||
case GR_GC_TRDY:
|
||||
aprint_normal("%d", 66);
|
||||
break;
|
||||
case GR_GC_STOP:
|
||||
aprint_normal("%d", 100);
|
||||
break;
|
||||
case GR_GC_STOP | GR_GC_TRDY:
|
||||
aprint_normal("%d", 133);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
aprint_normal("MHz PCI%s bus.", (gcreg & (GR_GC_DEVSEL | GR_GC_STOP | GR_GC_TRDY)) ? "-X" : "");
|
||||
} else {
|
||||
/* XXX - but only x1 devices so far */
|
||||
aprint_normal("PCI-Express x1 port.");
|
||||
}
|
||||
if (gcreg & GR_GC_3GBPS)
|
||||
aprint_normal(" 3.0Gb/s capable.\n");
|
||||
else
|
||||
aprint_normal("\n");
|
||||
|
||||
/* enable bus mastering in case the firmware didn't */
|
||||
csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
|
||||
csr |= PCI_COMMAND_MASTER_ENABLE;
|
||||
csr |= PCI_COMMAND_MEM_ENABLE;
|
||||
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr);
|
||||
|
||||
siisata_attach(sc);
|
||||
|
||||
if (!pmf_device_register(self, NULL, siisata_pci_resume))
|
||||
aprint_error_dev(self, "couldn't establish power handler\n");
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user