jmcneill a90447e255 Align addresses to cache lines in __clear_cache for aarch64. ... This corrects an issue where if the start and end address fall in different lines, and the end address is not cache line size aligned, the last line will not be invalidated properly. Patch from compiler-rt upstream: https://reviews.llvm.org/rCRT323315		2020-05-05 12:47:16 +00:00
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bsd	Align addresses to cache lines in __clear_cache for aarch64.	2020-05-05 12:47:16 +00:00
gpl2/dts	Define pinctrl-names for sdhci to fix it. From Harold Gutch and discussed	2020-02-22 09:54:27 +00:00
isc/atheros_hal	convert HAVE_GCC == 7 to HAVE_GCC >= 7.	2019-09-30 00:06:02 +00:00
mit/xen-include-public/dist/xen/include/public	revert previous, it actually doesn't help so no reason to diverge from xen	2020-04-19 11:01:35 +00:00