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Align addresses to cache lines in __clear_cache for aarch64.

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This corrects an issue where if the start and end address fall in different
lines, and the end address is not cache line size aligned, the last line
will not be invalidated properly.

Patch from compiler-rt upstream: https://reviews.llvm.org/rCRT323315
This commit is contained in:
jmcneill 2020-05-05 12:47:16 +00:00
parent 1d257e5525
commit a90447e255
1 changed files with 4 additions and 2 deletions
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6
sys/external/bsd/compiler_rt/dist/lib/builtins/clear_cache.c vendored
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@ -143,12 +143,14 @@ void __clear_cache(void *start, void *end) {
* uintptr_t in case this runs in an IPL32 environment.
*/
const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15);
for (addr = xstart; addr < xend; addr += dcache_line_size)
for (addr = xstart & ~(dcache_line_size - 1); addr < xend;
addr += dcache_line_size)
__asm __volatile("dc cvau, %0" :: "r"(addr));
__asm __volatile("dsb ish");
const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
for (addr = xstart; addr < xend; addr += icache_line_size)
for (addr = xstart & ~(icache_line_size - 1); addr < xend;
addr += icache_line_size)
__asm __volatile("ic ivau, %0" :: "r"(addr));
__asm __volatile("isb sy");
#elif defined(__sparc__)