A new "arm32_dma_range" structure now describes a DMA window, with
a system address base, bus address base, and length. In addition to
providing info about which memory regions are legal for DMA, the new
structure provides address translation support, as well.
As before, if a tag does not list any ranges, then all addresses are
considered valid, and no DMA address translation is performed.
This allows us to remove a large chunk of code which was duplicated and
tweaked slightly (to do the address translation) from the stock ARM
bus_dma in the XScale IOP and ARM Integrator ports.
Test compiled on all ARM platforms, test booted on Intel IQ80321 and Shark.
into platform-specific initialization code, giving platform-specific
code control over which free list a given chunk of memory gets put
onto.
Changes are essentially mechanical. Test compiled for all ARM
platforms, test booted on Intel IQ80321 and Shark.
Discussed some time ago on port-arm.
some systems chokes if the buffer is not 8-byte aligned. GCC only aligns
character arrays to 4-byte boundaries by default, so it's possible to get
unlucky and die in the boot blocks with a "kernel stack not valid halt".
Avoid the problem by using a local, aligned buffer as the argument to GET_ENV,
and copying the result into the caller's buffer.
Should fix PRs port-alpha/17682 and port-alpha/17717.
CVS ----------------------------------------------------------------------
Semiconductor Au1x00 series on-chip UARTs. Will be merged with
the original com.c driver once a few issues are tidied up. Main
differences from a standard 16550 UART are:
- separate rxdata and txdata registers
- single 16-bit register for the clock divisor
- "enable uart" register
devices. Currently the serial ports and ethernet MAC have working
drivers, and this has only been physically tested on the Au1000 CPU,
but these devices should work on the Au1100 and Au1500 CPUs too.
the virtual address for each DMA segment, just cache a pointer to the
original buffer/buftype used to load the DMA map, and use that. This
lets us shrink the bus_dma_segment_t down from 12 bytes to 8, and the
cache flushing is also more efficient.
Tested on an i80321 -- changes to others are mechanical.
Move call to sched_unlock_idle to later in the context switch to
eliminate a race where another processor could grab the outgoing
process before we were done saving our state into it, with predictable
results.
Bug spotted by Frank van der Linden <fvdl@wasabisystems.com>
also, don't re-enable interrupts temporarily in the middle of
switching to a new process, just wait until we're completely switched.
this didn't work on MP and it's not worth the effort.
