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Move the soft interrupts IPL masks from port-specific code to 

board-specific code.
Change a u_long to a uint32_t in the timer calibration routines.
This commit is contained in:
simonb 2002-07-29 16:21:03 +00:00
parent c61cf25192
commit 3f8c0bc7c5
2 changed files with 29 additions and 28 deletions
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21
sys/arch/evbmips/evbmips/interrupt.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: interrupt.c,v 1.2 2002/04/08 14:08:26 simonb Exp $ */
/* $NetBSD: interrupt.c,v 1.3 2002/07/29 16:21:03 simonb Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -48,20 +48,6 @@
#include <evbmips/evbmips/clockvar.h>
struct evbmips_soft_intrhand *softnet_intrhand;
/*
* This is a mask of bits to clear in the SR when we go to a
* given software interrupt priority level.
* Hardware ipls are port/board specific.
*/
const u_int32_t ipl_si_to_sr[_IPL_NSOFT] = {
MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */
MIPS_SOFT_INT_MASK_1, /* IPL_SOFTSERIAL */
};
struct evbmips_soft_intr evbmips_soft_intrs[_IPL_NSOFT];
struct evcnt mips_int5_evcnt =
@ -180,12 +166,13 @@ softintr_init(void)
for (i = 0; i < _IPL_NSOFT; i++) {
si = &evbmips_soft_intrs[i];
TAILQ_INIT(&si->softintr_q);
simple_lock_init(&si->softintr_slock);
si->softintr_ipl = IPL_SOFT + i;
evcnt_attach_dynamic(&si->softintr_evcnt, EVCNT_TYPE_INTR,
NULL, "soft", softintr_names[i]);
}
/* XXX Establish legacy soft interrupt handlers. */
/* XXX Establish legacy software interrupt handlers. */
softnet_intrhand = softintr_establish(IPL_SOFTNET,
(void (*)(void *))netintr, NULL);
@ -232,10 +219,12 @@ softintr_disestablish(void *arg)
int s;
s = splhigh();
simple_lock(&si->softintr_slock);
if (sih->sih_pending) {
TAILQ_REMOVE(&si->softintr_q, sih, sih_q);
sih->sih_pending = 0;
}
simple_unlock(&si->softintr_slock);
splx(s);
free(sih, M_DEVBUF);

36
sys/arch/evbmips/malta/malta_intr.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: malta_intr.c,v 1.3 2002/06/04 05:42:41 simonb Exp $ */
/* $NetBSD: malta_intr.c,v 1.4 2002/07/29 16:21:04 simonb Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
@ -62,29 +62,29 @@
* given hardware interrupt priority level.
*/
const u_int32_t ipl_sr_bits[_IPL_N] = {
0, /* IPL_NONE */
0, /* 0: IPL_NONE */
MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
MIPS_SOFT_INT_MASK_0, /* 1: IPL_SOFT */
MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
MIPS_SOFT_INT_MASK_0, /* 2: IPL_SOFTCLOCK */
MIPS_SOFT_INT_MASK_0|
MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */
MIPS_SOFT_INT_MASK_1, /* 3: IPL_SOFTNET */
MIPS_SOFT_INT_MASK_0|
MIPS_SOFT_INT_MASK_1, /* IPL_SOFTSERIAL */
MIPS_SOFT_INT_MASK_1, /* 4: IPL_SOFTSERIAL */
MIPS_SOFT_INT_MASK_0|
MIPS_SOFT_INT_MASK_1|
MIPS_INT_MASK_0, /* IPL_BIO */
MIPS_INT_MASK_0, /* 5: IPL_BIO */
MIPS_SOFT_INT_MASK_0|
MIPS_SOFT_INT_MASK_1|
MIPS_INT_MASK_0, /* IPL_NET */
MIPS_INT_MASK_0, /* 6: IPL_NET */
MIPS_SOFT_INT_MASK_0|
MIPS_SOFT_INT_MASK_1|
MIPS_INT_MASK_0, /* IPL_{TTY,SERIAL} */
MIPS_INT_MASK_0, /* 7: IPL_{TTY,SERIAL} */
MIPS_SOFT_INT_MASK_0|
MIPS_SOFT_INT_MASK_1|
@ -93,7 +93,19 @@ const u_int32_t ipl_sr_bits[_IPL_N] = {
MIPS_INT_MASK_2|
MIPS_INT_MASK_3|
MIPS_INT_MASK_4|
MIPS_INT_MASK_5, /* IPL_{CLOCK,HIGH} */
MIPS_INT_MASK_5, /* 8: IPL_{CLOCK,HIGH} */
};
/*
* This is a mask of bits to clear in the SR when we go to a
* given software interrupt priority level.
* Hardware ipls are port/board specific.
*/
const u_int32_t ipl_si_to_sr[_IPL_NSOFT] = {
MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */
MIPS_SOFT_INT_MASK_1, /* IPL_SOFTSERIAL */
};
struct malta_cpuintr {
@ -151,7 +163,7 @@ evbmips_intr_init(void)
void
malta_cal_timer(bus_space_tag_t st, bus_space_handle_t sh)
{
u_long ctrdiff[4], startctr, endctr;
uint32_t ctrdiff[4], startctr, endctr;
u_int8_t regc;
int i;
@ -212,7 +224,7 @@ malta_cal_timer(bus_space_tag_t st, bus_space_handle_t sh)
curcpu()->ci_cpu_freq *= 2;
#ifdef DEBUG
printf("Timer calibration: %lu cycles/sec [(%lu, %lu) * 16]\n",
printf("Timer calibration: %lu cycles/sec [(%u, %u) * 16]\n",
curcpu()->ci_cpu_freq, ctrdiff[2], ctrdiff[3]);
#endif
}