Commit Graph

15 Commits

Author SHA1 Message Date
scw d4f824014d A bunch of things:
- Clean up the way cpu-specific tlb/cache functions are configured
    and used.
  - Add a workaround for a problem whereby cpu* at superhyway? fails
    to probe.
  - Print more info about the cpu/cache.
  - Move the RESVEC handlers back into generic sh5 code and ditch
    the panic stack hack.
  - Make the on-chip SCIF device the default console on Cayman.
  - Add experimental support for booting via a standalone bootstrap
    program (not yet committed) and using the boot parameters passed
    in by it.
  - Add a few more SH elf constants.
  - Tick a couple of items off the TODO list.
2003-03-13 13:44:16 +00:00
scw c64b785002 Add sh5 kernel support for SAs.
This gets the Cayman to multi-user with a non-SA aware userland.
2003-01-19 19:49:47 +00:00
lukem 0635de35a3 Remove KDIR=, since SYS_INCLUDE=symlinks and KDIR are not supported any more. 2002-11-26 23:30:07 +00:00
scw 5f18a49912 Add alphaledio.h 2002-11-23 09:05:27 +00:00
scw a354470bbf Support for the alphanumeric LED display on the SuperH Cayman board. 2002-11-23 09:05:03 +00:00
scw c774ffbae4 MD glue for COMPAT_NETBSD32 on SH-5. 2002-10-23 13:26:35 +00:00
scw 251ba05b3f Support for the SH5 on-chip PCI bridge, and support for its deployment
in the Cayman board.
2002-09-28 11:16:36 +00:00
scw fe7de4db3f Need <machine/db_machdep.h> 2002-08-26 10:58:38 +00:00
briggs 0b956d0b8b Implement pmc(9) -- An interface to hardware performance monitoring
counters.  These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface.  Initially, the Intel XScale
counters are the only ones supported.
2002-08-07 05:14:47 +00:00
scw e9688612da Make it so kernels can be compiled for 32-bit or 64-bit with a
simple config file option.

Also, don't hard code the endian setting in a header file. Rely instead
on the compiler defining __LITTLE_ENDIAN__ and DTRT as appropriate.
2002-07-12 19:33:27 +00:00
scw e700a799a3 Follow convention for MACHINE_ARCH endian suffix. 2002-07-11 14:07:41 +00:00
scw 0b074fa253 SH5 floating point support, based on sh3. 2002-07-10 10:38:22 +00:00
scw ea38860915 SH5 profiling support. 2002-07-10 10:24:16 +00:00
scw 293298968a Descend into include subdirs and install relevant headers. 2002-07-10 08:56:11 +00:00
scw 59474a8c82 NetBSD, meet the SH-5 cpu.
SH-5, meet NetBSD.

Let's hope this is the start of a long and fruitful relationship. :-)

This code, funded by Wasabi Systems, adds initial support for the
Hitachi SuperH(tm) SH-5 cpu architecture to NetBSD.

At the present time, NetBSD/evbsh5 only runs on a SH-5 core simulator
which has no simulated devices other than a simple console. However, it
is good enough to get to the "root device: " prompt.

Device driver support for Real SH-5 Hardware is in place, particularly for
supporting the up-coming Cayman evaluation board, and should be quite
easy to get running when the hardware is available.

There is no in-tree toolchain for this port at this time. Gcc-current has
rudimentary SH-5 support but it is known to be buggy. A working toolchain
was obtained from SuperH to facilitate this port. Gcc-current will be
fixed in due course.

The SH-5 architecture is fully 64-bit capable, although NetBSD/evbsh5 has
currently only been tested in 32-bit mode. It is bi-endian, via a boot-
time option and it also has an "SHcompact" mode in which it will execute
SH-[34] user-land instructions.

For more information on the SH-5, see www.superh.com. Suffice to say it
is *not* just another respin of the SH-[34].
2002-07-05 13:31:28 +00:00