char *cpu_name(struct cpu_info *);
and use it when setting up the runq event counters, avoiding an 8 byte
kmem(4) allocation for each cpu. there are more places the cpuname is
used that can be converted to using this new interface, but that can
and will be done as future work.
as discussed with rmind.
- Reset GMII interface after wm_reset() in wm_init().
- Rework for assigning mii_{read,write}reg(). Use PCI product ID to identify
the PHY.
- Add code about LPLU(Low Power Link Up) function. Now we can linkup 1000BaseT
on PCH. It seems that we have to do the same work for ICH9.
for the patches!
I've lightly tested the basics: create cgd0 on vnd0d, initialize with
zeros, newfs /dev/cgd0a, mount, copy files on, unmount, drvctl -d
cgd0. Works fine. I also shutdown with a cgd0 configured: detached as
expected.
identified as product code 0x1533, which is what is actually in the
CS20. PCI_PRODUCT_ALI_M1543 was corrected recently and sio.c would fail
to match the bridge.
- save the strings passed to the mapping function so that they don't get
re-used. This leaks. To fix it properly we could either pass a flag to
free particular entries before re-using, or allocate all of them.
Allocating all of them wastes memory, allocating some of them makes
the code more complex.
This fixes compatibility binding (shell tab completion for example)
more closely match what is in the report. (This corrects the
off-by-one usages of most of the gray multimedia keys on a EX110
wireless keyboard so they can sensibly be used with libusbhid(3),
usbhidctl(1) and usbhidaction(1).)
This device also uses officially reserved usages (in the approximate
range of 0x1000 to 0x1100) in the Consumer usage page, but these
are out of the logical range the device reports as being valid.
- preallocate child struct, since the signal handler can be called before
wait_child, and we cannot allocate a child struct there. there is a signal
race still here if the program exits and the signal handler is called before
we allocate the struct.
Host Control Register (Offset 028h), the "Data Transfer Width" bit is in Host
Control Register (Offset 028h), not Power Control Register (Offset 029h).
