common across many of the 4xx parts. Leaves ibm405gp.h with device
address information specific to the 405GP CPU. Now allows opb.c to
support multiple 4xx CPU types.
documentation:
- Remove "mainbus" altogether.
- The new root is "plb" - the Processor Local Bus.
- Attached to this is the "opb" - the On-chip Peripheral Bus, to which
all the on-chip devices are attached (except the cpu and pci host
bridge).
- Port-specific code can pass an array of 'struct plb_dev' to
config_rootfound() to attach extra devices to the plb. The walnut
port attaches a "pbus" (Peripheral Bus) in here for the RTC and
pc keyboard controller to attach to.
There is still much 405GP specific code; the next round of changes will
generalise this to enable easier support for other 4xx CPUs.
MAC (emac). Much thanks to Jason Thorpe for debugging help writing this
driver. Tested on the walnut, and an earlier version of this driver works
on the OpenBlockSS.
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.
pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.
due to an AST. the rule is that we must always have interrupts
enabled when acquiring kernel_lock, so that we can process blocking IPIs
from another CPU which is already holding kernel_lock.
reduce differences between the MP and non-MP versions of this file.
on the non-boot CPUs, copy the L2CR configuration from the boot CPU.
also, fix the code that configures the L2 cache so that it works at all.
while I'm here, use mfspr() and mtspr() instead of inline asms.
Move call to sched_unlock_idle to later in the context switch to
eliminate a race where another processor could grab the outgoing
process before we were done saving our state into it, with predictable
results.
Bug spotted by Frank van der Linden <fvdl@wasabisystems.com>
also, don't re-enable interrupts temporarily in the middle of
switching to a new process, just wait until we're completely switched.
this didn't work on MP and it's not worth the effort.
data streams on execptions/interrupts since the processor will suspend
them for us. Only stop them on 1) process exit, 2) another process gets
its address space loaded, and 3) (for completeness only) we save a process's
AltiVec context.
remember the "exec"ness of a page. If a managed page is pmap_enter'ed
with VM_PROT_EXECUTE, remember that it's an "exec"page. Such that when
additional mapping are performed, no synch'ing of the I-cache is needed.
Revoke "exec"ness when the page is mapped into the kernel with VM_PROT_WRITE
or the pmap_page_protect is called with VM_PROT_NONE.
simonb