Commit Graph

1294 Commits

Author SHA1 Message Date
simonb
f41231cffc Fix the order of the CPU revision and company options fields in the cpu
table for the Alchemy CPUs; successfully recognises an Au1500 now.
2002-09-09 03:42:04 +00:00
simonb
54ef88d289 In the idle functions, set curproc to NULL and (#ifdef LOCKDEBUG) call
sched_unlock_idle before enabling interrupts.  LOCKDEBUG kernels now
boot successfully.

Thanks to Chris Gilbert for helping fix this.
2002-09-09 02:32:38 +00:00
simonb
378a5c4c85 Include "opt_lockdebug.h" here to #ifdef LOCKDEBUG actually does something. 2002-09-09 01:03:10 +00:00
gehenna
77a6b82b27 Merge the gehenna-devsw branch into the trunk.
This merge changes the device switch tables from static array to
dynamically generated by config(8).

- All device switches is defined as a constant structure in device drivers.

- The new grammer ``device-major'' is introduced to ``files''.

	device-major <prefix> char <num> [block <num>] [<rules>]

- All device major numbers must be listed up in port dependent majors.<arch>
  by using this grammer.

- Added the new naming convention.
  The name of the device switch must be <prefix>_[bc]devsw for auto-generation
  of device switch tables.

- The backward compatibility of loading block/character device
  switch by LKM framework is broken. This is necessary to convert
  from block/character device major to device name in runtime and vice versa.

- The restriction to assign device major by LKM is completely removed.
  We don't need to reserve LKM entries for dynamic loading of device switch.

- In compile time, device major numbers list is packed into the kernel and
  the LKM framework will refer it to assign device major number dynamically.
2002-09-06 13:18:43 +00:00
gmcgarry
1a8058823b RAS support for MIPS. Tested on R3000. 2002-08-28 08:34:06 +00:00
simonb
993a94e6bc Add the Toshiba TX4927 CPU. 2002-08-28 02:09:29 +00:00
simonb
0702d44ac5 Fix printf format string for the EXTENT_DEBUG case. 2002-08-19 12:03:48 +00:00
simonb
771cbe3e84 Remove CPU_MIPS_DOUBLE_COUNT for the MIPS 20Kc - it's cycle counter runs
at the normel CPU frequency.
2002-08-19 12:03:04 +00:00
simonb
7e0228bbc3 Update to rev 1.48 from Algorithmics; adds BONITO64 register definitions. 2002-08-18 16:00:33 +00:00
simonb
fd2320f396 Issue a dummy read after a write to the BONITO_PCIMAP_CFG register to
make sure the write is posted; needed to keep the BONITO64 happy.
2002-08-18 15:57:55 +00:00
briggs
0b956d0b8b Implement pmc(9) -- An interface to hardware performance monitoring
counters.  These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface.  Initially, the Intel XScale
counters are the only ones supported.
2002-08-07 05:14:47 +00:00
shin
b0d22e8404 fix CPU_ROOT_DEVICE implementation. 2002-08-06 06:54:36 +00:00
shin
a59d490375 * add CPU_MIPS_NO_LLSC to Toshiba TX3912, TX3922, TX3927.
* fix mips_has_llsc calculation logic.
2002-08-05 13:02:40 +00:00
shin
2f33f11745 ++CPU_MAXID for CPU_LLSC. 2002-08-05 13:00:47 +00:00
simonb
f068458085 The TX79 core in the R5900 doesn't support LL/SC.
XXX: Others in this table will need to be updated.
2002-08-05 02:18:43 +00:00
simonb
fef76c7e26 Use a __HAVE_BOOTINFO_H define to check for bootinfo support instead of
speading port names in arch-dependant code.
2002-08-05 02:13:14 +00:00
gmcgarry
460c8c3adc mipsco and sgimips also implement bootinfo, but didn't provide
the CPU_BOOTED_KERNEL sysctl variable.
2002-08-04 03:16:19 +00:00
gmcgarry
7470337484 Move LLSC feature test for mips1 to cputab[]. 2002-08-04 02:27:51 +00:00
gmcgarry
617f58fb55 Add sysctl variable to represent native CPU support for LL/SC instructions. 2002-08-04 01:47:15 +00:00
gmcgarry
886e32d355 mips1 doesn't have native LL/SC instructions. 2002-08-04 01:43:03 +00:00
gmcgarry
3647e0d293 Merge cpu_sysctl() for all mips ports, based on powerpc and m68k precedent.
For now, only pmax implements CPU_BOOTED_KERNEL.  Need to revisit.
2002-08-04 01:41:23 +00:00
simonb
e5a27ab142 Sync bcm1250 headers with cfe-1.0.32. 2002-07-31 06:26:24 +00:00
simonb
e9dfdd9b2e Add support for the watchdog timers on the BCM1xxx parts. 2002-07-31 05:30:20 +00:00
simonb
314a0f00d1 Fix the mask for the watchdog init and count registers. 2002-07-30 23:10:04 +00:00
simonb
c38f2b0214 Remove some debug code accidently left in. 2002-07-29 16:25:02 +00:00
simonb
223e50d28e Add a slightly modified dev/ic/com.c that supports the Alchemy
Semiconductor Au1x00 series on-chip UARTs.  Will be merged with
the original com.c driver once a few issues are tidied up.  Main
differences from a standard 16550 UART are:
 - separate rxdata and txdata registers
 - single 16-bit register for the clock divisor
 - "enable uart" register
2002-07-29 15:42:41 +00:00
simonb
ca42af5e80 Add support for the the Alchemy Semiconductor Au1x00 series on-chip
devices.  Currently the serial ports and ethernet MAC have working
drivers, and this has only been physically tested on the Au1000 CPU,
but these devices should work on the Au1100 and Au1500 CPUs too.
2002-07-29 15:39:11 +00:00
itojun
f8e5e9c295 be friendly with gcc-3.1.1 -O2, which takes advantage of ANSI C
pointer aliasing rule (gcc optimization/7427).  from tsubai, sync w/kame
2002-07-29 09:14:36 +00:00
simonb
328bb37293 Add support for detecting Alchemy Semiconductor CPUs. Alchemy use the
processor ID field to donote the CPU core revision and the company
options field do donate the SOC chip type, so we need to add an extra
field to the "pridtab" structure to identify these CPUs.
2002-07-26 00:43:54 +00:00
gmcgarry
2e0c7e68a5 Implement true LL/SC emulation. Mostly from Jason Thorpe in PR17548. 2002-07-21 05:47:51 +00:00
simonb
bfbb000051 White space nits, add a #endif comment. 2002-07-19 03:13:55 +00:00
gmcgarry
cc4037a913 Overhaul the emulation facility. We do this by:
- accumulating all emulation code (including floating-point) in one place
- steal MachFPInterrupt() back from SOFTFLOAT for use only with interrupts
  and traps from *real* FPUs
- introducing MachEmulateInst() as a common dispatch point for all
  emulated instructions
- cleaning up emulation dispatch in trap()

Also, while we're here, implement MIPS2 LL/SC/SYNC emulation for MIPS1.

Tested on r3k with and without SOFTFLOAT enabled.
2002-07-06 23:59:18 +00:00
thorpej
011d4d5f44 Add kernel support for having userland provide the signal trampoline:
* struct sigacts gets a new sigact_sigdesc structure, which has the
  sigaction and the trampoline/version.  Version 0 means "legacy kernel
  provided trampoline".  Other versions are coordinated with machine-
  dependent code in libc.
* sigaction1() grows two more arguments -- the trampoline pointer and
  the trampoline version.
* A new __sigaction_sigtramp() system call is provided to register a
  trampoline along with a signal handler.
* The handler is no longer passed to sensig() functions.  Instead,
  sendsig() looks up the handler by peeking in the sigacts for the
  process getting the signal (since it has to look in there for the
  trampoline anyway).
* Native sendsig() functions now select the appropriate trampoline and
  its arguments based on the trampoline version in the sigacts.

Changes to libc to use the new facility will be checked in later.  Kernel
version not bumped; we will ride the 1.6C bump made recently.
2002-07-04 23:32:02 +00:00
thorpej
bf7d5bca07 Eliminate 4 unused sigframe members. 2002-07-04 19:20:01 +00:00
simonb
a441a7dffa Remove some clocktick debug code. 2002-06-27 04:09:15 +00:00
simonb
7471732325 Add the 20Kc processor ID. 2002-06-27 03:43:45 +00:00
simonb
8e38e28f7f White space nits: space after a comma. 2002-06-24 05:52:28 +00:00
simonb
d4068eac65 Add 64MB and 256MB tlb page masks. 2002-06-24 05:46:47 +00:00
manu
d0c5097f05 Typo 2002-06-23 20:36:36 +00:00
simonb
4cf248e04b Fix tyop. 2002-06-17 22:48:45 +00:00
christos
3b50728cf4 MD systrace gluons. 2002-06-17 16:32:57 +00:00
simonb
4d304073f1 Add some ifdef's around the usage of mips_wait_idle; fixes builds for
playstations2 and MIPS1-only kernels.
Based on patch from Bill Squier.
2002-06-07 02:05:22 +00:00
simonb
e36c88d696 Introduce CHIP_ACCESSTYPE which (if defined) is used as the type for
performing the accesses, regardless of the size of the data type
requested.  Useful for chips which require fixed-width accesses to all
registers.

Cast arguments printed using %lx to u_long all the time, not just
sometimes.

Include a few extra files here so they don't need to be included by the
files that include this one.
2002-06-05 06:27:10 +00:00
simonb
8492ceb1ff White space nits. 2002-06-05 06:09:28 +00:00
simonb
db50a069f8 Remove an ELF-related comment that isn't needed any more. 2002-06-05 06:02:52 +00:00
simonb
2100183aff For the CP0 status register bit definitions- add the MX, PX and NMI bits
and rename TLB_SHUTDOWN and SOFT_RESET to TS and SR (the abbreviations
in the MIPS documentation).

XXX: this file really needs to be cleaned up one day...
2002-06-05 05:56:48 +00:00
thorpej
04076e5943 Make this work with an ISO C preprocessor. 2002-06-04 21:44:40 +00:00
thorpej
d941ddfee0 Don't use -traditional-cpp if HAVE_GCC3. 2002-06-04 21:39:09 +00:00
simonb
f4e42e7eb6 Add an extremely rough SMBus handler and RTC driver. This will be
cleaned up significantly when we have an MI SMBus framework, but at
least we can see the RTC on the swarm now.
2002-06-04 08:32:41 +00:00
simonb
9cc65a96d0 3 ports are now using the reciprocal count divisor code now, move it
to <mips/cpu.h>, and add MIPS_SET_CI_RECIPRICAL and MIPS_COUNT_TO_MHZ
macros to use it.
2002-06-04 05:42:41 +00:00