Commit Graph

18 Commits

Author SHA1 Message Date
thorpej 15dcb4a98e Link the kernel at 1MB. 2001-08-22 19:44:47 +00:00
thorpej 17c22a634f Set PCI_NETBSD_ENABLE_IDE to 0x01, so that the first IDE channel
will be enabled.
2001-08-22 00:42:43 +00:00
tsutsui df016928f8 Remove (commented out) ncr* at pci? lines. 2001-07-07 17:09:47 +00:00
thorpej 3ae8717568 Add commented-out examples for how to use MEMSIZE and ETHADDR options
in the event that you need them (really old PMON versions).  Add FDESC.
Comment out SCSI-related stuff until I work out why the system goes into
outer orbit when its enabled.
2001-06-22 14:15:56 +00:00
thorpej 04986e1e9a Add FDESC. 2001-06-22 14:14:16 +00:00
thorpej 306b1b09bc Kernel config file for a P-6032. 2001-06-22 14:12:19 +00:00
thorpej 36a4b627d0 Sigh, Jason needs to go to sleep. 2001-06-22 07:00:25 +00:00
thorpej 32e780695d Add a couple of missing p6032 bits. 2001-06-22 06:50:21 +00:00
thorpej 0c37c9e860 Check in work-in-progress of P-6032 support. This is not tested,
but is meant for back-up purposes.
2001-06-22 06:02:54 +00:00
thorpej 4c73c770ce Add MEMSIZE and ETHADDR options, so that they can be set in
the kernel config file, in case you have a buggy PMON which
doesn't provide the environment variables to the kernel.
2001-06-14 16:14:37 +00:00
thorpej 7e59a1be7a No longer need MIPS3_5200 here. 2001-06-12 22:32:50 +00:00
thorpej 82418a77b0 Add PCMCIA devices. 2001-06-10 08:45:09 +00:00
thorpej ce66bf0803 Rewrite the interrupt handling code:
- Compute the number of CPU pipeline cycles per second using the
  mc146818.
- Use the COMPARE interrupt for the hardclock interrupt.
- Collapse all interrupt priorities into a single priority, and use
  the CPU interrupt inputs to determine the interrupt source (local
  device, PCI device, ISA device, etc.)

This allows us to have interrupt sharing.
2001-06-10 05:26:58 +00:00
thorpej 0e82abb5de Add MIPS3_5200. 2001-06-10 05:02:33 +00:00
thorpej 71cb790fb5 Add support for the Algorithmics P-4032 board. This is totally
untested, since I have no P-4032 board, but it's no worse than
the current situation, which is "totally non-working P-4032
support in the ARC port, of all places".
2001-06-01 16:00:03 +00:00
thorpej 356699e86b Fat-trimming. 2001-06-01 15:30:11 +00:00
thorpej f4f6c1dd1c Enable SCSI. 2001-06-01 03:53:29 +00:00
thorpej 16b9c60621 A port to the Algorithmics MIPS evaluation boards. We currently
support the P-5064, which has a QED RM5xxx CPU soldered on.

There is some skeletal support for the P-4032 (an older board, which
had an R4xxx CPU).  There are some placeholders for the P-6032, which
is their newest board, but no real code yet (the P-6032 has a different
PCI controller, the Algorithmics BONITO).

There are still some (apprently softintr-related) problems with the
algor kernel, but it works well-enough to self-host.

Kudos to Allegro Networks for loaning me a P-5064 board on which to do
the port.
2001-05-28 16:22:13 +00:00