* We could overrun the eva by as much as L1SEG_SIZE-PAGE_SIZE.
* sva was advanced *twice* for each valid l3 or l2 page, causing it to get out
of sync with the PTE pointers.
"To fully support self-modifying code in any situation, it is imperative that
a CPUSHA intrcution is executed before the execution of the first self-modified
instruction. The CPUSHA instruction has the effect of ensuring that there is
no stale data iin memory, the pipeline is flushed, and instruction prefetches
are repeated and taken from external memory."
I verified that this is the only way (I can think of) to make the sigtramp
regression test work on 68040. doing cpushl dc; cinvl ic; over the affected
address range, then nop (to synchronize the pipeline) is not enough; apparently
the nop does not FLUSH the pipeline and prefetch...
Note that the 68060 UM has copied the above cited passage, but in fact this is
not true. This might be connected to the fact that the 68060 does ensure
memory access order under most conditions.
- in sbus_get_intr(), if we are not an onboard device (ie, sbus card),
encode the slot number into the sbi_pri so that we can later extract
it and use it to find the interrupt map & clear registers for this
device.
- remove "intr" support as it is really pre-sun4u only.
- don't "pause" for so long in sbus interrupt debug messages..
with the slot number being passed back from sbus_get_intr(), the FS/BE
card in an ultra2 now appears to get interrupts and gets beyond
waiting for the scsibus probe!
stub for memsize_bitmap() to use the PROM bitmap for memory information.
Add a memsize function pointer to the platform structure, and make all
existing DECstation models use memsize_scan() for now.
Interestingly, from the Ultrix cpuconf.{c,h} only the 3100 and 5400 use
a memory scan to determine available memory - all other models use the
PROM bitmap...
that should make it clear in which slot the card is expected to be in.
Isapnp is not what it seems to be on the atari (where interrupts are
hardwired to slot numbers).
remove GENERIC.v6 file (as it is part of GENERIC now).
"faith" interface is commented out by default as it is not really for
general use.
IPsec items are commented out as well, though we can enable "options IPSEC"
without export-related issue ("options IPSEC" will enable authentication
portion only). We may need to think about it again.
if you have problem compiling with INET6 on archs I do not have access to,
please contact me.
XXX what to do with arch/arm32/SHARK{,.v6}?
IBM WorkPad z50
NEC MobilePro 770, 800
Sharp Tripad PV6000 / Vadem Clio
NEC MC-CS series
Fujitsu Intertop CX300
change keyboard layout according to model(default).
add options PCKBD_LAYOUT to override default.
>split the "asc" and "tcds" searching into two separate sections and
>keep a "tcdsdev" of the booted tcds device. make sure that the "asc"
>is the child of the tcds. this fixes boot device detection on dec
>5000/400 (prolly 400-900) machines in the presense of a tcds option
>card, which would use the right tcds chip & disk scsiid of the last
>attached tcds -- which meant it would choose the wrong disk, or not
>find the boot device at all if the corresponding scsiid was unused in
>the last attached disk.
>
>XXX: this may need to be copied to dec_3000_300.c but i have no idea
>as i can not test this hardware at all...
>
>fixes PR#8771 by myself.
keep a "tcdsdev" of the booted tcds device. make sure that the "asc"
is the child of the tcds. this fixes boot device detection on dec
5000/400 (prolly 400-900) machines in the presense of a tcds option
card, which would use the right tcds chip & disk scsiid of the last
attached tcds -- which meant it would choose the wrong disk, or not
find the boot device at all if the corresponding scsiid was unused in
the last attached disk.
XXX: this may need to be copied to dec_3000_300.c but i have no idea
as i can not test this hardware at all...
fixes PR#8771 by myself.
Shuichiro URATA <ur@a-r.org> makes kernel softfloat emulation code.
http://www.a-r.org/~ur/softfloat1116.diff.gz
is Patch for
sys/arch/mips/conf/files.mips
sys/arch/mips/mips/fp.S
sys/arch/mips/mips/fpemu.c
sys/arch/mips/mips/genassym.cf
sys/arch/mips/mips/locore.S
sys/arch/mips/mips/mips_machdep.c
sys/arch/mips/mips/process_machdep.c
sys/arch/mips/mips/trap.c
sys/arch/mips/mips/vm_machdep.c
After apply this patch,pmax package binary works on hpcmips!
entries for the IRQs used by the IDE controller, which aren't really
PCI IRQs (they're ISA compat IRQs), and thus have link values that
don't make a lot of sense.
patches, cleaned up and heavily reworked by me. Basic algorithm is
the same, although the code structure is now quite different.
Main differences:
- Initialization path is totally different.
- We use the `compat router' information, if present, to determine which
PCI ICU driver we should use.
- Fixup configuration headers on devices not on bus 0.
out from UCHIYAMA Yasushi's PCI BIOS patches, and fairly heavily reworked
by me.
Main differences:
- Only use the PCI BIOS to get the config mechanism and interrupt routing
info for now. No need to use the BIOS for PCI config access right now,
since the old mechanism works fine, and this keeps the code smaller.
- PCI BIOS initialization code path is much different.
- Always use the $PIR table if it exists, and only fallback to the
PCI BIOS 2.1 GetInterruptRouting call if it's not there.
This module does not include any of the fixup code; that is coming
in separate commits.
simonb