ITE IT8368E PCMCIA controller
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sys/arch/hpcmips/dev/it8368.c
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728
sys/arch/hpcmips/dev/it8368.c
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/* $NetBSD: it8368.c,v 1.1 1999/11/21 06:48:58 uch Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include "opt_tx39_debug.h"
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#include "opt_it8368debug.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/bus.h>
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#include <dev/pcmcia/pcmciareg.h>
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#include <dev/pcmcia/pcmciavar.h>
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#include <dev/pcmcia/pcmciachip.h>
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#include <hpcmips/tx/tx39var.h>
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#include <hpcmips/tx/txcsbusvar.h>
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#include <hpcmips/dev/it8368reg.h>
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#ifdef IT8368DEBUG
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#define DPRINTF(arg) printf arg
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#else
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#define DPRINTF(arg)
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#endif
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#undef IT8368_POWERSUPPORT /* XXX don't work FIXME */
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int it8368e_match __P((struct device*, struct cfdata*, void*));
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void it8368e_attach __P((struct device*, struct device*, void*));
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int it8368_print __P((void*, const char*));
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int it8368_submatch __P((struct device*, struct cfdata*, void*));
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struct it8368e_softc {
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struct device sc_dev;
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struct device *sc_pcmcia;
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tx_chipset_tag_t sc_tc;
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void *sc_ih;
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/* Register space */
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bus_space_tag_t sc_csregt;
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bus_space_handle_t sc_csregh;
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/* I/O, attribute space */
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bus_space_tag_t sc_csiot;
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bus_space_handle_t sc_csioh;
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bus_addr_t sc_csiobase;
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bus_size_t sc_csiosize;
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/* XXX theses means attribute memory. not memory space. memory space is 0x64000000. */
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bus_space_tag_t sc_csmemt;
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bus_space_handle_t sc_csmemh;
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bus_addr_t sc_csmembase;
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bus_size_t sc_csmemsize;
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/* Separate I/O and attribute space mode */
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int sc_fixattr;
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/* Card interrupt handler */
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int sc_card_irq;
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int (*sc_card_fun) __P((void*));
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void *sc_card_arg;
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void *sc_card_ih;
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};
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void it8368_attach_socket __P((struct it8368e_softc*));
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void it8368_access __P((struct it8368e_softc*, int, int));
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int it8368_intr __P((void*));
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int it8368_insert_intr __P((void*));
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int it8368_remove_intr __P((void*));
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void it8368_intr_ack __P((struct it8368e_softc*));
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void it8368_dump __P((struct it8368e_softc*));
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int it8368_chip_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, struct pcmcia_mem_handle*));
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void it8368_chip_mem_free __P((pcmcia_chipset_handle_t, struct pcmcia_mem_handle*));
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int it8368_chip_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, bus_size_t, struct pcmcia_mem_handle*, bus_addr_t*, int*));
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void it8368_chip_mem_unmap __P((pcmcia_chipset_handle_t, int));
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int it8368_chip_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, bus_size_t, bus_size_t, struct pcmcia_io_handle*));
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void it8368_chip_io_free __P((pcmcia_chipset_handle_t, struct pcmcia_io_handle*));
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int it8368_chip_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, bus_size_t, struct pcmcia_io_handle*, int*));
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void it8368_chip_io_unmap __P((pcmcia_chipset_handle_t, int));
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void it8368_chip_socket_enable __P((pcmcia_chipset_handle_t));
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void it8368_chip_socket_disable __P((pcmcia_chipset_handle_t));
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void *it8368_chip_intr_establish __P((pcmcia_chipset_handle_t, struct pcmcia_function*, int, int (*) (void*), void*));
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void it8368_chip_intr_disestablish __P((pcmcia_chipset_handle_t, void*));
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static struct pcmcia_chip_functions it8368_functions = {
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it8368_chip_mem_alloc,
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it8368_chip_mem_free,
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it8368_chip_mem_map,
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it8368_chip_mem_unmap,
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it8368_chip_io_alloc,
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it8368_chip_io_free,
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it8368_chip_io_map,
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it8368_chip_io_unmap,
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it8368_chip_intr_establish,
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it8368_chip_intr_disestablish,
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it8368_chip_socket_enable,
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it8368_chip_socket_disable
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};
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struct cfattach it8368e_ca = {
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sizeof(struct it8368e_softc), it8368e_match, it8368e_attach
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};
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/*
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* IT8368 configuration register is big-endian.
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*/
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static u_int16_t it8368_reg_read __P((bus_space_tag_t, bus_space_handle_t, int));
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static void it8368_reg_write __P((bus_space_tag_t, bus_space_handle_t, int, u_int16_t));
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int
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it8368e_match(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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return 1;
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}
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void
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it8368e_attach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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struct cs_attach_args *ca = aux;
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struct it8368e_softc *sc = (void*)self;
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tx_chipset_tag_t tc;
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bus_space_tag_t csregt;
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bus_space_handle_t csregh;
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u_int16_t reg;
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printf(" ");
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sc->sc_tc = tc = ca->ca_tc;
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sc->sc_csregt = csregt = ca->ca_csreg.cstag;
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bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize,
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0, &sc->sc_csregh);
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csregh = sc->sc_csregh;
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sc->sc_csiot = ca->ca_csio.cstag;
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sc->sc_csiobase = ca->ca_csio.csbase;
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sc->sc_csiosize = ca->ca_csio.cssize;
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#ifdef WINCE_DEFAULT_SETTING
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#warning WINCE_DEFAULT_SETTING
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#else
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it8368_dump(sc); /* print WindowsCE setting */
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/* LHA[14:13] <= HA[14:13] */
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reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
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reg &= ~IT8368_CTRL_ADDRSEL;
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it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
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/* Set all MFIO direction as LHA[23:13] output pins */
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reg = it8368_reg_read(csregt, csregh, IT8368_MFIODIR_REG);
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reg |= IT8368_MFIODIR_MASK;
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it8368_reg_write(csregt, csregh, IT8368_MFIODIR_REG, reg);
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/* Set all MFIO functions as LHA */
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reg = it8368_reg_read(csregt, csregh, IT8368_MFIOSEL_REG);
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reg &= ~IT8368_MFIOSEL_MASK;
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it8368_reg_write(csregt, csregh, IT8368_MFIOSEL_REG, reg);
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/* Disable MFIO interrupt */
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reg = it8368_reg_read(csregt, csregh, IT8368_MFIOPOSINTEN_REG);
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reg &= ~IT8368_MFIOPOSINTEN_MASK;
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it8368_reg_write(csregt, csregh, IT8368_MFIOPOSINTEN_REG, reg);
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reg = it8368_reg_read(csregt, csregh, IT8368_MFIONEGINTEN_REG);
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reg &= ~IT8368_MFIONEGINTEN_MASK;
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it8368_reg_write(csregt, csregh, IT8368_MFIONEGINTEN_REG, reg);
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/* Port direction */
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reg = IT8368_PIN_CRDVCCON1 | IT8368_PIN_CRDVCCON0 |
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IT8368_PIN_CRDVPPON1 | IT8368_PIN_CRDVPPON0 |
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IT8368_PIN_BCRDRST;
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it8368_reg_write(csregt, csregh, IT8368_GPIODIR_REG, reg);
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/* Interrupt */
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reg = IT8368_PIN_CRDSW | IT8368_PIN_CRDDET2 | IT8368_PIN_CRDDET1 | /* CSC */
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IT8368_PIN_BCRDRDY; /* #IREQ */
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/*
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* Enable negative edge only.
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*/
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it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg);
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it8368_reg_write(csregt, csregh, IT8368_GPIOPOSINTEN_REG, 0);
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/* Clear interrupt */
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it8368_intr_ack(sc);
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#endif /* WINCE_DEFAULT_SETTING */
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/*
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* Separate I/O and attribute memory region
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*/
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reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
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reg |= IT8368_CTRL_FIXATTRIO;
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it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
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if (IT8368_CTRL_FIXATTRIO & it8368_reg_read(csregt, csregh, IT8368_CTRL_REG)) {
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sc->sc_fixattr = 1;
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printf(":fix attr mode\n");
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sc->sc_csmemt = sc->sc_csiot;
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sc->sc_csiosize /= 2;
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sc->sc_csmemsize = sc->sc_csiosize;
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sc->sc_csmembase = sc->sc_csiosize;
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} else {
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printf(":legacy attr mode\n");
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sc->sc_fixattr = 0;
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sc->sc_csmemt = sc->sc_csiot;
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sc->sc_csmemh = sc->sc_csmemh;
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sc->sc_csmembase = sc->sc_csiobase;
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sc->sc_csmemsize = sc->sc_csiosize;
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}
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it8368_dump(sc);
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it8368_chip_socket_enable(sc);
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/*
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* CSC interrupt (IO bit1 5:8/1) XXX this is something bogus.
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*/
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tx_intr_establish(tc, ca->ca_irq1, IST_EDGE, IPL_TTY, it8368_insert_intr, sc);
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tx_intr_establish(tc, ca->ca_irq2, IST_EDGE, IPL_TTY, it8368_remove_intr, sc);
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/*
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* Card interrupt (3:2)
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*/
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sc->sc_card_irq = ca->ca_irq3;
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printf("\n");
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it8368_attach_socket(sc);
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}
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static u_int16_t
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it8368_reg_read(t, h, ofs)
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bus_space_tag_t t;
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bus_space_handle_t h;
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int ofs;
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{
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u_int16_t val;
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val = bus_space_read_2(t, h, ofs);
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return 0xffff & (((val >> 8) & 0xff)|((val << 8) & 0xff00));
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}
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static void
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it8368_reg_write(t, h, ofs, v)
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bus_space_tag_t t;
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bus_space_handle_t h;
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int ofs;
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u_int16_t v;
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{
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u_int16_t val;
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val = 0xffff & (((v >> 8) & 0xff)|((v << 8) & 0xff00));
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bus_space_write_2(t, h, ofs, val);
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}
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void
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it8368_intr_ack(sc)
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struct it8368e_softc *sc;
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{
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bus_space_tag_t csregt = sc->sc_csregt;
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bus_space_handle_t csregh = sc->sc_csregh;
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/* Clear interrupt */
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it8368_reg_write(csregt, csregh, IT8368_GPIOPOSINTSTAT_REG,
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it8368_reg_read(csregt, csregh, IT8368_GPIOPOSINTSTAT_REG));
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it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG,
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it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTSTAT_REG));
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it8368_reg_write(csregt, csregh, IT8368_MFIOPOSINTSTAT_REG,
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it8368_reg_read(csregt, csregh, IT8368_MFIOPOSINTSTAT_REG));
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it8368_reg_write(csregt, csregh, IT8368_MFIONEGINTSTAT_REG,
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it8368_reg_read(csregt, csregh, IT8368_MFIONEGINTSTAT_REG));
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}
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int
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it8368_insert_intr(arg)
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void *arg;
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{
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/* not coded yet */
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printf("[CSC insert]\n");
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return it8368_intr(arg);
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}
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int
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it8368_remove_intr(arg)
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void *arg;
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{
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/* not coded yet */
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printf("[CSC remove]\n");
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return it8368_intr(arg);
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}
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#define LIMIT_GPIO 12
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#define LIMIT_MFIO 10
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#define PRINTGPIO(m) __bitdisp(it8368_reg_read(csregt, csregh, IT8368_GPIO##m##_REG), 0, LIMIT_GPIO, #m, 1)
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#define PRINTMFIO(m) __bitdisp(it8368_reg_read(csregt, csregh, IT8368_MFIO##m##_REG), 0, LIMIT_MFIO, #m, 1)
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int
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it8368_intr(arg)
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void *arg;
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{
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struct it8368e_softc *sc = arg;
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#if 0
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bus_space_tag_t csregt = sc->sc_csregt;
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bus_space_handle_t csregh = sc->sc_csregh;
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PRINTGPIO(POSINTSTAT);
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PRINTGPIO(NEGINTSTAT);
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#endif
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it8368_intr_ack(sc);
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/* Dispatch card interrupt handler */
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if (sc->sc_card_fun) {
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(*sc->sc_card_fun)(sc->sc_card_arg);
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}
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return 0;
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}
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int
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it8368_print(arg, pnp)
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void *arg;
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const char *pnp;
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{
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if (pnp) {
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printf("pcmcia at %s", pnp);
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}
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return UNCONF;
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}
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int
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it8368_submatch(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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return ((*cf->cf_attach->ca_match)(parent, cf, aux));
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}
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void
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it8368_attach_socket(sc)
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struct it8368e_softc *sc;
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{
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struct pcmciabus_attach_args paa;
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paa.paa_busname = "pcmcia";
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paa.pct = (pcmcia_chipset_tag_t)&it8368_functions;
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paa.pch = (pcmcia_chipset_handle_t)sc;
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paa.iobase = 0; /* I don't use them */
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paa.iosize = 0;
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if ((sc->sc_pcmcia = config_found_sm((void*)sc, &paa, it8368_print,
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it8368_submatch))) {
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/* XXX Check card here XXX */
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pcmcia_card_attach(sc->sc_pcmcia);
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}
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}
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void *
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it8368_chip_intr_establish(pch, pf, ipl, ih_fun, ih_arg)
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pcmcia_chipset_handle_t pch;
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struct pcmcia_function *pf;
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int ipl;
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int (*ih_fun) __P((void *));
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void *ih_arg;
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{
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struct it8368e_softc *sc = (struct it8368e_softc*) pch;
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tx_chipset_tag_t tc = sc->sc_tc;
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if (sc->sc_card_fun) {
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panic("it8368_chip_intr_establish: duplicate card interrupt handler.");
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}
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sc->sc_card_fun = ih_fun;
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sc->sc_card_arg = ih_arg;
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if (!(sc->sc_card_ih =
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tx_intr_establish(tc, sc->sc_card_irq, IST_EDGE, IPL_BIO,
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it8368_intr, sc))) {
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printf("it8368_chip_intr_establish: can't establish.\n");
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return 0;
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}
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return sc->sc_card_ih;
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}
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void
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it8368_chip_intr_disestablish(pch, ih)
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pcmcia_chipset_handle_t pch;
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void *ih;
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{
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struct it8368e_softc *sc = (struct it8368e_softc*) pch;
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if (!sc->sc_card_fun) {
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panic("it8368_chip_intr_disestablish: no handler established.");
|
||||
}
|
||||
|
||||
sc->sc_card_fun = 0;
|
||||
sc->sc_card_arg = 0;
|
||||
|
||||
tx_intr_disestablish(sc->sc_tc, ih);
|
||||
}
|
||||
|
||||
int
|
||||
it8368_chip_mem_alloc(pch, size, pcmhp)
|
||||
pcmcia_chipset_handle_t pch;
|
||||
bus_size_t size;
|
||||
struct pcmcia_mem_handle *pcmhp;
|
||||
{
|
||||
struct it8368e_softc *sc = (struct it8368e_softc*) pch;
|
||||
it8368_access(sc, 0, 0);
|
||||
|
||||
pcmhp->memt = sc->sc_csmemt;
|
||||
|
||||
if (bus_space_map(sc->sc_csmemt, sc->sc_csmembase, size, 0,
|
||||
&pcmhp->memh)) {
|
||||
return 1;
|
||||
}
|
||||
pcmhp->addr = pcmhp->memh;
|
||||
pcmhp->size = size;
|
||||
pcmhp->realsize = size;
|
||||
DPRINTF(("it8368_chip_mem_alloc %#x+%#x\n", pcmhp->memh, size));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
it8368_chip_mem_free(pch, pcmhp)
|
||||
pcmcia_chipset_handle_t pch;
|
||||
struct pcmcia_mem_handle *pcmhp;
|
||||
{
|
||||
bus_space_unmap(pcmhp->memt, pcmhp->memh, pcmhp->size);
|
||||
}
|
||||
|
||||
int
|
||||
it8368_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp)
|
||||
pcmcia_chipset_handle_t pch;
|
||||
int kind;
|
||||
bus_addr_t card_addr;
|
||||
bus_size_t size;
|
||||
struct pcmcia_mem_handle *pcmhp;
|
||||
bus_addr_t *offsetp;
|
||||
int *windowp;
|
||||
{
|
||||
struct it8368e_softc *sc = (struct it8368e_softc*) pch;
|
||||
|
||||
it8368_access(sc, 0, 0);
|
||||
|
||||
pcmhp->memt = sc->sc_csmemt;
|
||||
pcmhp->addr = pcmhp->memh;
|
||||
pcmhp->size = size;
|
||||
pcmhp->realsize = size;
|
||||
*offsetp = 0;
|
||||
DPRINTF(("it8368_chip_mem_map %#x+%#x\n", pcmhp->memh, size));
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
it8368_chip_mem_unmap(pch, window)
|
||||
pcmcia_chipset_handle_t pch;
|
||||
int window;
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
it8368_access(sc, io, width)
|
||||
struct it8368e_softc *sc;
|
||||
int io;
|
||||
int width;
|
||||
{
|
||||
#if not_required_yet
|
||||
txreg_t reg32;
|
||||
|
||||
reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG);
|
||||
if (io && width == 1) {
|
||||
reg32 |= TX39_MEMCONFIG3_PORT8SEL;
|
||||
} else {
|
||||
reg32 &= ~TX39_MEMCONFIG3_PORT8SEL;
|
||||
}
|
||||
if (!sc->sc_fixattr) {
|
||||
if (io) {
|
||||
reg32 |= TX39_MEMCONFIG3_CARD1IOEN;
|
||||
} else {
|
||||
reg32 &= ~TX39_MEMCONFIG3_CARD1IOEN;
|
||||
}
|
||||
}
|
||||
tx_conf_write(sc->sc_tc, TX39_MEMCONFIG3_REG, reg32);
|
||||
|
||||
reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG);
|
||||
if (!(reg32 & TX39_MEMCONFIG3_CARD1IOEN))
|
||||
printf("CARDIOEN failed\n");
|
||||
if (!(reg32 & TX39_MEMCONFIG3_PORT8SEL))
|
||||
printf("PORT8SEL failed\n");
|
||||
|
||||
delay(20);
|
||||
#endif
|
||||
}
|
||||
|
||||
int
|
||||
it8368_chip_io_alloc(pch, start, size, align, pcihp)
|
||||
pcmcia_chipset_handle_t pch;
|
||||
bus_addr_t start;
|
||||
bus_size_t size;
|
||||
bus_size_t align;
|
||||
struct pcmcia_io_handle *pcihp;
|
||||
{
|
||||
struct it8368e_softc *sc = (struct it8368e_softc*) pch;
|
||||
|
||||
it8368_access(sc, 1, 0);
|
||||
|
||||
if (start) {
|
||||
if (bus_space_map(sc->sc_csiot, start, size, 0, &pcihp->ioh)) {
|
||||
return 1;
|
||||
}
|
||||
DPRINTF(("it8368_chip_io_alloc map port %#x+%#x\n",
|
||||
start, size));
|
||||
} else {
|
||||
if (bus_space_alloc(sc->sc_csiot, sc->sc_csiobase,
|
||||
sc->sc_csiobase + sc->sc_csiosize, size,
|
||||
align, 0, 0, &pcihp->addr, &pcihp->ioh)) {
|
||||
return 1;
|
||||
}
|
||||
pcihp->flags = PCMCIA_IO_ALLOCATED;
|
||||
DPRINTF(("it8368_chip_io_alloc alloc %#x from %#x\n",
|
||||
size, pcihp->addr));
|
||||
|
||||
}
|
||||
pcihp->iot = sc->sc_csiot;
|
||||
pcihp->size = size;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
it8368_chip_io_map(pch, width, offset, size, pcihp, windowp)
|
||||
pcmcia_chipset_handle_t pch;
|
||||
int width;
|
||||
bus_addr_t offset;
|
||||
bus_size_t size;
|
||||
struct pcmcia_io_handle *pcihp;
|
||||
int *windowp;
|
||||
{
|
||||
struct it8368e_softc *sc = (struct it8368e_softc*) pch;
|
||||
|
||||
it8368_access(sc, 1, 0);
|
||||
|
||||
pcihp->iot = sc->sc_csiot;
|
||||
pcihp->addr = pcihp->ioh + offset;
|
||||
pcihp->size = size;
|
||||
DPRINTF(("it8368_chip_io_map %#x:%#x+%#x\n", pcihp->ioh, offset, size));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
it8368_chip_io_free(pch, pcihp)
|
||||
pcmcia_chipset_handle_t pch;
|
||||
struct pcmcia_io_handle *pcihp;
|
||||
{
|
||||
if (pcihp->flags & PCMCIA_IO_ALLOCATED) {
|
||||
bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size);
|
||||
} else {
|
||||
bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size);
|
||||
}
|
||||
DPRINTF(("it8368_chip_io_free %#x+%#x\n", pcihp->ioh, pcihp->size));
|
||||
}
|
||||
|
||||
void
|
||||
it8368_chip_io_unmap(pch, window)
|
||||
pcmcia_chipset_handle_t pch;
|
||||
int window;
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
it8368_chip_socket_enable(pch)
|
||||
pcmcia_chipset_handle_t pch;
|
||||
{
|
||||
struct it8368e_softc *sc = (struct it8368e_softc*)pch;
|
||||
bus_space_tag_t csregt = sc->sc_csregt;
|
||||
bus_space_handle_t csregh = sc->sc_csregh;
|
||||
volatile u_int16_t reg;
|
||||
#ifdef IT8368_POWERSUPPORT
|
||||
/* Disable card */
|
||||
reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
|
||||
reg &= ~IT8368_CTRL_CARDEN;
|
||||
it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
|
||||
delay(20000);
|
||||
|
||||
/* Power off */
|
||||
reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);
|
||||
reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK);
|
||||
reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V);
|
||||
it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);
|
||||
delay(20000);
|
||||
|
||||
/*
|
||||
* wait 300ms until power fails (Tpf). Then, wait 100ms since
|
||||
* we are changing Vcc (Toff).
|
||||
*/
|
||||
delay((300 + 100) * 1000);
|
||||
|
||||
/* Supply Vcc */
|
||||
reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);
|
||||
reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK);
|
||||
reg |= IT8368_PIN_CRDVCC_5V; /* XXX */
|
||||
it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);
|
||||
|
||||
/*
|
||||
* wait 100ms until power raise (Tpr) and 20ms to become
|
||||
* stable (Tsu(Vcc)).
|
||||
*
|
||||
* some machines require some more time to be settled
|
||||
* (300ms is added here).
|
||||
*/
|
||||
delay((100 + 20 + 300) * 1000);
|
||||
|
||||
/* Enable card and interrupt driving. */
|
||||
reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
|
||||
reg |= (IT8368_CTRL_GLOBALEN | IT8368_CTRL_CARDEN);
|
||||
reg |= IT8368_CTRL_FIXATTRIO; /* XXX */
|
||||
it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
|
||||
delay(200000);
|
||||
|
||||
/* Assert reset signal */
|
||||
reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);
|
||||
reg |= IT8368_PIN_BCRDRST;
|
||||
it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);
|
||||
/*
|
||||
* hold RESET at least 10us.
|
||||
*/
|
||||
delay(10);
|
||||
/* Dessert reset signal */
|
||||
reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);
|
||||
reg &= ~IT8368_PIN_BCRDRST;
|
||||
it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);
|
||||
delay(20000);
|
||||
|
||||
DPRINTF(("socket enabled\n"));
|
||||
it8368_dump(sc);
|
||||
#else
|
||||
/* Enable card and interrupt driving. */
|
||||
reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
|
||||
reg |= (IT8368_CTRL_GLOBALEN | IT8368_CTRL_CARDEN);
|
||||
it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
|
||||
delay(200000);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
it8368_chip_socket_disable(pch)
|
||||
pcmcia_chipset_handle_t pch;
|
||||
{
|
||||
#ifdef IT8368_POWERSUPPORT
|
||||
struct it8368e_softc *sc = (struct it8368e_softc*) pch;
|
||||
bus_space_tag_t csregt = sc->sc_csregt;
|
||||
bus_space_handle_t csregh = sc->sc_csregh;
|
||||
u_int16_t reg;
|
||||
|
||||
/* Disable card */
|
||||
reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
|
||||
reg &= ~IT8368_CTRL_CARDEN;
|
||||
it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
|
||||
delay(20000);
|
||||
|
||||
/* Power down */
|
||||
reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);
|
||||
reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK);
|
||||
reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V);
|
||||
it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);
|
||||
delay(20000);
|
||||
|
||||
/*
|
||||
* wait 300ms until power fails (Tpf).
|
||||
*/
|
||||
delay(300 * 1000);
|
||||
DPRINTF(("socket disabled\n"));
|
||||
it8368_dump(sc);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
it8368_dump(sc)
|
||||
struct it8368e_softc *sc;
|
||||
{
|
||||
#ifdef IT8368DEBUG
|
||||
bus_space_tag_t csregt = sc->sc_csregt;
|
||||
bus_space_handle_t csregh = sc->sc_csregh;
|
||||
|
||||
printf("[GPIO]\n");
|
||||
PRINTGPIO(DIR);
|
||||
PRINTGPIO(DATAIN);
|
||||
PRINTGPIO(DATAOUT);
|
||||
PRINTGPIO(POSINTEN);
|
||||
PRINTGPIO(NEGINTEN);
|
||||
PRINTGPIO(POSINTSTAT);
|
||||
PRINTGPIO(NEGINTSTAT);
|
||||
printf("[MFIO]\n");
|
||||
PRINTMFIO(SEL);
|
||||
PRINTMFIO(DIR);
|
||||
PRINTMFIO(DATAIN);
|
||||
PRINTMFIO(DATAOUT);
|
||||
PRINTMFIO(POSINTEN);
|
||||
PRINTMFIO(NEGINTEN);
|
||||
PRINTMFIO(POSINTSTAT);
|
||||
PRINTMFIO(NEGINTSTAT);
|
||||
__bitdisp(it8368_reg_read(csregt, csregh, IT8368_CTRL_REG), 0, 15, "CTRL", 1);
|
||||
__bitdisp(it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG), 8, 11, "]CRDDET/SENSE[", 1);
|
||||
#endif
|
||||
}
|
||||
102
sys/arch/hpcmips/dev/it8368reg.h
Normal file
102
sys/arch/hpcmips/dev/it8368reg.h
Normal file
@ -0,0 +1,102 @@
|
||||
/* $NetBSD: it8368reg.h,v 1.1 1999/11/21 06:48:59 uch Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1999, by UCHIYAMA Yasushi
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. The name of the developer may NOT be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* ITE IT8368E PCMCIA/GPIO Buffer Chip
|
||||
* http://www.ite.com/tw/mobile/it8368v07.pdf
|
||||
*/
|
||||
#define IT8368_GPIODATAOUT_REG 0x00
|
||||
#define IT8368_MFIODATAOUT_REG 0x02
|
||||
#define IT8368_GPIODIR_REG 0x04
|
||||
#define IT8368_MFIODIR_REG 0x06
|
||||
#define IT8368_MFIOSEL_REG 0x0a
|
||||
#define IT8368_GPIODATAIN_REG 0x0c
|
||||
#define IT8368_MFIODATAIN_REG 0x0e
|
||||
#define IT8368_GPIOPOSINTEN_REG 0x10
|
||||
#define IT8368_MFIOPOSINTEN_REG 0x12
|
||||
#define IT8368_GPIONEGINTEN_REG 0x14
|
||||
#define IT8368_MFIONEGINTEN_REG 0x16
|
||||
#define IT8368_GPIOPOSINTSTAT_REG 0x18
|
||||
#define IT8368_MFIOPOSINTSTAT_REG 0x1a
|
||||
#define IT8368_GPIONEGINTSTAT_REG 0x1c
|
||||
#define IT8368_MFIONEGINTSTAT_REG 0x1e
|
||||
#define IT8368_CTRL_REG 0x20
|
||||
|
||||
#define IT8368_GPIODATAOUT_MASK 0x1fff
|
||||
#define IT8368_MFIODATAOUT_MASK 0x07ff
|
||||
#define IT8368_GPIODIR_MASK 0x1fff
|
||||
#define IT8368_MFIODIR_MASK 0x07ff
|
||||
|
||||
#define IT8368_MFIOSEL_VGAEN 0x0800
|
||||
#define IT8368_MFIOSEL_MASK 0x07ff
|
||||
#define IT8368_GPIODATAIN_MASK 0x1fff
|
||||
#define IT8368_MFIODATAIN_MASK 0x07ff
|
||||
#define IT8368_GPIOPOSINTEN_MASK 0x1fff
|
||||
#define IT8368_MFIOPOSINTEN_MASK 0x07ff
|
||||
#define IT8368_GPIONEGINTEN_MASK 0x1fff
|
||||
#define IT8368_MFIONEGINTEN_MASK 0x07ff
|
||||
#define IT8368_GPIOPOSINTSTAT_MASK 0x1fff
|
||||
#define IT8368_MFIOPOSINTSTAT_MASK 0x07ff
|
||||
#define IT8368_GPIONEGINTSTAT_MASK 0x1fff
|
||||
#define IT8368_MFIONEGINTSTAT_MASK 0x07ff
|
||||
|
||||
|
||||
#define IT8368_CTRL_FIXATTRIO 0x8000
|
||||
#define IT8368_FIXATTR_OFFSET 0x02000000
|
||||
#define IT8368_FIXIO_OFFSET 0x0
|
||||
#define IT8368_FIXIOATTR_SIZE 0x02000000
|
||||
|
||||
#define IT8368_CTRL_ADDRSEL 0x0010
|
||||
#define IT8368_CTRL_BYTESWAP 0x0008
|
||||
#define IT8368_CTRL_CARDEN 0x0004
|
||||
#define IT8368_CTRL_GLOBALEN 0x0002
|
||||
#define IT8368_CTRL_INTTRIEN 0x0001
|
||||
|
||||
#define IT8368_PIN_CRDSW 0x1000
|
||||
#define IT8368_PIN_CRDDET2 0x0800
|
||||
#define IT8368_PIN_CRDDET1 0x0400
|
||||
#define IT8368_PIN_CRDSENSE2 0x0200
|
||||
#define IT8368_PIN_CRDSENSE1 0x0100
|
||||
#define IT8368_PIN_CRDVCCON1 0x0080
|
||||
#define IT8368_PIN_CRDVCCON0 0x0040
|
||||
#define IT8368_PIN_CRDVPPON1 0x0020
|
||||
#define IT8368_PIN_CRDVPPON0 0x0010
|
||||
#define IT8368_PIN_BCRDWP 0x0008
|
||||
#define IT8368_PIN_BCRDRDY 0x0004
|
||||
#define IT8368_PIN_BCRBVD2 0x0002
|
||||
#define IT8368_PIN_BCRDRST 0x0001
|
||||
|
||||
#define IT8368_PIN_CRDVCCMASK 0x00c0
|
||||
#define IT8368_PIN_CRDVPPMASK 0x0030
|
||||
#define IT8368_PIN_CRDVCC_0V 0x0000
|
||||
#define IT8368_PIN_CRDVCC_3V IT8368_PIN_CRDVCCON0
|
||||
#define IT8368_PIN_CRDVCC_5V IT8368_PIN_CRDVCCON1
|
||||
#define IT8368_PIN_CRDVPP_0V 0x0000
|
||||
#define IT8368_PIN_CRDVPP_CRDVCC IT8368_PIN_CRDVPPON0
|
||||
#define IT8368_PIN_CRDVCC_12V IT8368_PIN_CRDVPPON1
|
||||
#define IT8368_PIN_CRDVCC_HIZ (IT8368_PIN_CRDVPPON0|IT8368_PIN_CRDVPPON1)
|
||||
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Reference in New Issue
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