- We check PHY register read error correctly (timeout and NFE_PHY_ERROR), so
don't check NFE_PHY_DATA register's value with 0xffffffff or 0. At least,
some registers may have 0.
- Check NFE_PHY_ERROR bit in nfe_miibus_writereg().
- Improve debug printf
is detected:
- If DATA64_EN isn't set in CFG after a reset, don't use 64-bit data path
at all (it's been disabled by an EEPROM setting).
- Provide a hook for force-disabling the 64-bit data path.
- Otherwise, perform the "known 64-bit cards" check as done previously
(because dodgy-vendor-EEPROM-settings still applies).
- On some variations, the internal PHY is ghosted at #0 and #1. Work
around this by ignoring PHY #0 accesses unless we don't find one, and
then look for one there as a fall-back if we don't detect anything else.
- Fix access width when setting the TxDMAUrgentThresh register.
- Support MBUFTRACE.
check from a (soft) interrupt handler. But if a platform does not otherwise
require the pmap_tlb_miss_lock, then where will be a brief window of
inconsistency that, while harmless, will still fire an assertion in the
consistency check.
Fix this with the following changes:
1- Refactor the pmap_tlb_miss_lock into MI code and rename it from
pmap_tlb_miss_lock_{enter,exit}() to pmap_tlb_miss_lock_{enter,exit}().
MD code can still define the "md" hooks as necessary, and if so, will
override the common implementation.
2- Provde a pmap_bootstrap_common() function to perform common pmap bootstrap
operations, namely initializing the pmap_tlb_miss_lock if it's needed.
If MD code overrides the implementation, it's responsible for initializing
its own lock.
3- Call pmap_bootstrap_common() from the mips, powerpc booke, and riscv
pmap_bootstrap() routines. (This required adding one for riscv.)
4- Switch powerpc booke to the common pmap_tlb_miss_lock.
5- Enable pmap_tlb_miss_lock if DEBUG is defined, even if it's not otherwise
required.
PR port-mips/55062 (Failed assertion in pmap_md_tlb_check_entry())
