a47891200f
fixed DMACSR_BITS definition to reflect DMACSR_READ bit renaming
1999-08-28 09:42:44 +00:00
3c215084bc
discovered the purpose of another bit in the dma control register.
...
DMACSR_READ is now a CSR status bit which can be used to know if current transfer is
from cpu to device.
the old DMACSR_READ bit is renamed DMACSR_SETREAD. This is a control bit that tells
the dma transfer to be from cpu to device.
1999-08-28 09:19:04 +00:00
00c8d4dd90
changed dma start alignment from 4 to 16 so that the cache flush
...
functions always have cache line aligned segments.
continued experimentation with scsi driver.
1999-03-14 10:31:05 +00:00
ba3bedf25e
After some experimentation, now allow dma start alignment to be 4.
...
Removed separate alignment constant for ethernet since it appears to
be unnecessary.
1998-12-27 09:03:14 +00:00
84676442e2
Commented out some bus_dma code, until I can fix.
...
(bus_dma.c needs sync with alpha port!)
Continued progress on scsi driver.
A couple of other compiler warning level of tweaks.
1998-07-19 21:41:16 +00:00
ddff5f8e94
Initial import of NetBSD/next68k.
1998-06-09 07:53:05 +00:00
dbj