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262 Commits

Author SHA1 Message Date
jonathan 2d10220f8f Yet more mips1/mips3 merging: 
Move mips-specific pmap definitions (PMAP_PREFER for mips3, declaratin
of pmap_bootstrap() for the system-specific machdep.c) from
arch/pmax/include/pmap.h to arch/mips/include/pmap.h.
 1997-06-16 07:47:42 +00:00
jonathan df6533a42e Fix idempotent inclusion test macro: _MACHCONST -> _MIPS_CPUREGS_H_ 
to avoid collision with obsolete Sprite-derived NetBSD/pica  header file.
 1997-06-16 07:41:08 +00:00
jonathan 5db35a8cce Yet more merging: 
* Move declaration of locore communcation variables (CPU family,
     cache sizes, etc) to mips/include/locore.h.  Delete from
     pmax/include/cpu.h and older versions from pica/include/cpu.h.

   * Move definitions of CLKF_BASEPRI, CLKF_USERMODE to mips/include/cpu.
   * Delete duplicate definitions in pica/include/cpu.h, pmax/include/cpu.h.
 1997-06-16 06:17:25 +00:00
jonathan 8ccf9122e4 Garbage-collect MIPS_3K_xxx, MIPS_4K_xxx outidde mips/include/cpuregs.h: 
MIPS_3K_xxx ->    MIPS1_xxx
    MIPS_4K_xxx ->    MIPS3_xxx
 1997-06-16 05:37:32 +00:00
jonathan 59c33b9f85 Garbage-collect #include <machine/machConst.h>. 1997-06-16 03:52:37 +00:00
jonathan d3ecedb9fb Garbage-collect non-jumptable prototype for wbflush(). 1997-06-16 03:52:08 +00:00
jonathan 2557a6fa43 GC more old header files: 
<machine/locore.h> -> <mips/locore.h>
    <machine/mips_opcode.h> -> <mips/mips_opcode..h>
 1997-06-16 03:29:07 +00:00
jonathan 2520d0a604 Remove genassym.c. (pmax has used genassym.cf for some time.) 1997-06-16 02:58:28 +00:00
jonathan c6b9463cd1 Remove all references to <machine/machAsmDefs.h>. 
Use #include <mips/asm.h> instead.
 1997-06-16 01:23:56 +00:00
jonathan 15628b2d97 Move merged pmax psl.h with mips1/mips3 support to mips/include/psl.h. 
Change pmax/include/psl.h to just do #include <mips/psl.h>.

pmax/include/psl.h would go away completely if it wasn't stil required
by compat/common/kern_exit_43.c.
 1997-06-16 01:10:03 +00:00
jonathan 8e5f767c50 Use generic MIPS pmap vm_machdep.c 1997-06-16 00:35:10 +00:00
jonathan 747e2b5e7e Generic mips pmap/vm code: move the merged pmax mips1/mips3 vm_machdep 
and pmap code to arch/mips/mips.
Use <mips/XXX.h> header files, not <machine/XXX.h>.
 1997-06-16 00:16:08 +00:00
mhitch ab0eff4a87 From Toru Nishimura: _FORKBRAINDAMAGE is gone, user process entered through 
proc_trampoline().
More merged MIPS1/MIPS3 support.
 1997-06-15 18:21:17 +00:00
mhitch f42f8eb4e6 More merged MIPS1/MIPS3 support - from pica pmap.c 1997-06-15 18:19:47 +00:00
mhitch 76f5c2a6c6 More merged MIPS1/MIPS3 support for DECstations. 1997-06-15 18:02:20 +00:00
mhitch 6b75aad4ca From Toru Nishimura: exception trapframe changes, separate out syscall 
processing from generic trap processing,  _FORKBRAINDAMAGE is gone -
user process entered through proc_trampoline(), mini-debugger from pica
port.
More merged MIPS1/MIPS3 support for DECstations.
 1997-06-15 17:49:53 +00:00
mhitch a5c7f52094 More merged MIPS1/MIPS3 support. Added wbflush() and proc_trampoline() to 
locore vector.  Display level 2 (secondary) cache size.
 1997-06-15 17:47:46 +00:00
mhitch 6748462623 From Toru Nishimura: _FORKBRAINDAMAGE is gone, user process entered through 
proc_trampoline(); move away from UADDR access to user structure.
From Toru Nishimura:  exception trapframe changes, mini-debugger from pica
port, separate out syscall exception.
DECstation MIPS3 support: wbflush() is cpu-dependent, MIPS3 level 2 cache
support.
 1997-06-15 17:44:46 +00:00
mhitch 501b5e6892 From Toru Nishimura: adjust for struct user pcb changes. 1997-06-15 17:40:03 +00:00
mhitch 386cf35c8d From Toru Nishimura: exception trapframe changes. 1997-06-15 17:37:45 +00:00
mhitch 27f717cdb8 From Toru Nishimura: user pcb/proc changes for exception handling and 
removing access through UADDR.
 1997-06-15 17:36:24 +00:00
mhitch ffb95ac852 DECstation MIPS3 support: wbflush() is cpu-dependent, need declaration from 
machine/locore.h.
From Toru Nishimura: _FORKBRAINDAMAGE is gone, user process entered through
proc_trampoline() [also cpu-dependent].
 1997-06-15 17:33:53 +00:00
mhitch 75b0c4777c From Toru Nishimura: _FORKBRAINDAMAGE is gone, user process entered through 
proc_trampoline().
 1997-06-15 17:28:46 +00:00
mhitch c06eb27dc9 More merged MIPS1/MIPS3 support: still only allows single-architecture 
support.
 1997-06-15 17:27:03 +00:00
mhitch fb6d59052e More merged MIPS1/MIPS3 support. The pte definitions still need work before 
they can be support both MIPS1 and MIPS3.
 1997-06-15 17:24:22 +00:00
jonathan 070deac2d1 Use standard symbolic register names in stacktrace() and logstacktrace(). 1997-06-15 01:18:25 +00:00
jonathan 8e854e11d1 Rewrite stack traceback printing (stacktrace()) and logging(logstacktrace() 
wrappers for stacktrace_subr() in assembly code to avoid prototype conflicts.
 1997-06-15 01:08:16 +00:00
mrg dc6a98e92c bring mrg-vm-swap2 onto mainilne. 1997-06-12 15:09:23 +00:00
jonathan f89e57aee7 Add sys_sysarch() calls for the standard mips userspace cache-control calls. 1997-06-09 11:46:16 +00:00
jonathan 19e4111ef7 Move the mips sys_machdep.c from pmax/pmax to mips/mips, to enforce a 
common sysarch on all mips ports.
 1997-06-09 02:14:56 +00:00
jonathan d6a4dfdc41 Declarations for standard MIPS-ABI cacheflush() and cachectl() calls, 
as used by g++ trampoline code.
 1997-06-08 10:52:04 +00:00
jonathan f15c808e44 Initialize machine_arch from MACHINE_ARCH. 1997-06-08 10:48:02 +00:00
jonathan ccc08d5a61 Move MACHINE_ARCH and _MACHINE_ARCH from pmax/include/param.h to 
mips/include/mips_param.h.  (They should be common to all mips ports.)
 1997-06-08 10:46:01 +00:00
veego de7e49a954 Add 'char machine_arch[] = "xxx";' for the new sysctl hw.machine_arch. 1997-06-06 23:26:01 +00:00
jonathan 6aa07ba92c Add #ifdef _KERNEL/#endif around prototype of mips single-step emulator. 
Add "struct proc;" inside the ifdef: <sys/proc.h> includes <machine/proc.h>
before declaring struct proc.
 1997-06-02 01:58:38 +00:00
jonathan ed8e9558ab Lint: printf formats inside #ifdef DEBUG (long vs int, %x vs pointer). 
Add XXX to inconsistency: sometimes pmap.c calls blkclr(), sometimes it uses
an inline C loop tuned for 4-entry writebuffer.  Why?
 1997-05-26 23:02:11 +00:00
jonathan 333ebdebd6 lint: prototype blkclr __P((caddr_t val, int size)). Used in pmap code. 1997-05-25 23:00:40 +00:00
jonathan dbdac42c7e Add ecoff symbol header definitions for mips1. 1997-05-25 21:22:19 +00:00
jonathan 2548f9ceee lint: add prototype for kvtophys(). 1997-05-25 10:16:17 +00:00
jonathan e991c94232 Add parens where requested by gcc -Wall. 1997-05-25 10:01:38 +00:00
jonathan 94d7e627c1 Rename cpu_singlstep() to mips_singlestep() and add prototype. 
(it's not part of the standard interface to MD code.)

XXX Consider moving into process_machdep.c when the mips3 changes are merged.
 1997-05-25 09:56:45 +00:00
jonathan cedd6dbe25 Lint: move forward declarations to beginning of file and protoize. 
delete unused variables and add redundant parens where suggested.
 1997-05-25 05:19:51 +00:00
jonathan d5b9a48fd5 Add prototype for cpu_exec_ecoff_setregs() to mips/inuclde/ecoff_machdep.h. 
Use it in compat/ultrix/ultrix_misc.c (setting emul type on mips).
 1997-05-24 10:26:30 +00:00
jonathan b14cdadc36 lint: Create mips/include/conf.h with prototypes for {mem device. 
Add 'struct proc *p' 4th arg to mmopen(), mmclose().
      Delete unused variable.
 1997-05-24 08:57:59 +00:00
jonathan aab81e72b8 lint: add prototypes for interrupt(), softintr(), pppintr(). 1997-05-24 08:49:22 +00:00
jonathan ba1c517a52 GNU ld script for linking mips kernels, contributed by Arne Juul. 1997-05-23 22:21:06 +00:00
jonathan ba2aa6f75a Add cpu_spl[012345]() definitions to locore. These clear the given 
interrupt-enable bit in the status register, and all lower bits.

Can be used for spl{bio,net,tty,clock,statclock} on machines where
devices are wried to mips hard-interrupt levels in ascending bit order
so as to match the BSD spl.9 ordering.
 1997-05-19 23:25:09 +00:00
jonathan 0a995f71a2 Fix typo. 1997-05-19 21:24:10 +00:00
mhitch 8e9925b45b Eliminate vm_pmap. 1997-05-18 17:26:30 +00:00
jonathan ac99526674 Add defines for increasing SPL levels, assuming devices are wired up 
in to CPU interrupt pins in order of increasing priority.
 1997-05-18 03:19:41 +00:00