values).
Implement a secondary connection-reestablishement mode, which is only
entered after (1) we have successfully transfered payload data over this
connection and (2) if initial retries did not reestablish a session.
In this mode we retry (infrequently) forever, until adminstrator stops
us (by "ifconfig ppppoe0 down"). XXX - need to display this mode in
pppoectl.
It is now possible to pull the DSL modems plug for say 15 minutes, plug
it back in again and just wait. The connection will be reestablished within
three minutes.
pull-up/pull-down registers if you turn on verbose output.
And moved softc structure definition from vrgiuvar.h to vrgiu.c, which was
needless in other parts of kernel.
thus isolating the "iffy hueristic" from the rest of the relocation code.
* In the "iffy hueristic", use _GOT_END_, not _DYNAMIC.
* Include the addend in Alpha R(RELATIVE) relocations.
parameters from first principles rather than using a static table for some
rates. This makes it work correctly on ARM7500, for which the table was
bogus (ARM7500 has a different refclk from VIDC20).
of this file in the master FSF sources; I obviously disagree
with the change, since it was apparently made to appease one
particular OS, even though previous binutils releases had been
made with ENTRY=__start, and have brought it up on
binutils@sources.redhat.com).
podulebus Ethernet cards. This replaces the NE2000 memory-access routines
with ones that don't try to transfer more than 255 bytes at a time.
This code should perhaps be merged into ne2000.c, but presumably most NE2000
clones won't need it.
during BUS_DMASYNC_PREREAD.
Fixes problem where SCSI bus probe didn't read meaningful identity data.
Technically there should be no difference between invalidating before or
after the DMA, but for reasons known only to the R3000 this fixes the
problem. Some thought needs to be given to whether there is a performace
difference between these two cases.
left out as it was a no-op on the R3000 processor. However, recent changes
to the Mips cache ops highlighted we should DTRT in case the MI/MD layer
choses to invalidate the cache ahead of the DMA instead of after it.
