Commit Graph

62695 Commits

Author SHA1 Message Date
nakayama
da6c94469a Fix (unused) pstate mask bits in tstate and comment. 2016-05-18 07:59:30 +00:00
palle
2f23095fbd sun4v: Implement missng MMU protection trap handling - mostly from OpenBSD 2016-05-17 19:43:28 +00:00
palle
61ea5f5e14 Update TODO: sun4v_datatrap handling for trap level 0 is working 2016-05-17 19:39:44 +00:00
msaitoh
7ca43d6799 Fix CORTEXA9Rx definitions. 2016-05-17 08:27:24 +00:00
ryo
ec48232126 Add initial support for Freescale i.MX7 SoC and
Atmark Techno Armadillo-IoT G3 boards.

Contributed by Internet Initiative Japan Inc.
2016-05-17 06:44:45 +00:00
christos
10c1bb4dec Clamt the PAX_ASLR random value to the max bits we have for VA. 2016-05-17 00:39:43 +00:00
palle
ef44ed55df Avoid assembler-specific defines by using the export keyword in genassym.cf instead 2016-05-16 20:03:07 +00:00
maxv
9c4befc9b2 Update kern.ldscript.4MB. It is the same as kern.ldscript, but with a large
page alignment before rodata.
2016-05-16 07:52:31 +00:00
nakayama
49bc961c13 %g1 is not preserved across function call, so load it before
return_from_trap.
2016-05-15 23:54:58 +00:00
chs
6ee802c24a define ALTENTRY(), needed by dtrace. 2016-05-15 15:26:04 +00:00
maxv
9aca421dba Explicitly mention MP_TRAMPOLINE in these comments, so that NXR links them. 2016-05-15 10:35:54 +00:00
maxv
4c1aaf9dc6 Split the PRELOADED_MODULES+BOOTSTRAP_TABLES chunk into two separate
chunks mapped independently with RWX and RW, on both amd64 and i386.

This way the BOOTSTRAP TABLES are non-executable.
2016-05-15 07:17:53 +00:00
maxv
0d0621d260 Reduce the diff between amd64 and i386. We invert two instructions on
amd64, but it makes no difference since PDE_SIZE = 8.
2016-05-15 07:01:36 +00:00
christos
931302e025 Turn on MPROTECT on GENERIC and both MPROTECT and ASLR on XEN* 2016-05-14 17:11:30 +00:00
maxv
b561cb98a5 KNF so it appears aligned on NXR, and fix a comment. 2016-05-14 12:48:31 +00:00
maxv
8f728b8ede Actually, put the NOX identification above. Old CPUs do not support the
cpuid instruction.
2016-05-14 09:51:56 +00:00
maxv
15756d7e09 The NOX bit on large pages does not need to be amd64-specific anymore.
The i386 secondary CPUs can now properly handle it.
2016-05-14 09:37:21 +00:00
maxv
f63de3d1a3 Map rodata and data+bss independently, and give them R and RW with
fillkpt_nox. The code is exactly the same as amd64's.
2016-05-14 08:49:16 +00:00
maxv
e39b2c82ed Define fillkpt_nox on i386, same as amd64.
But there is a difference in the way it is done here. If PAE is not enabled,
PDE_SIZE = 4, so there is no NOX bit set. If PAE is enabled, PDE_SIZE = 8,
so the NOX bit is set.

This works exactly as intended, since NOX does not exist in the non-PAE
case.
2016-05-14 08:39:41 +00:00
maxv
9d6cfafacd Fix the secondary CPUs bug in i386. Same as amd64. 2016-05-14 08:34:00 +00:00
maxv
3b5965adb8 Align the segments on i386. We're going to map them independently. 2016-05-14 08:19:42 +00:00
maxv
60dc596ebe Define killkpt, and don't use _RELOC. Same as amd64. 2016-05-14 06:49:34 +00:00
palle
f985c2c1eb sun4v: add missing implementation of sun4v_datatrap_tl0 so data_access_fault() is called - mostly from OpenBSD 2016-05-13 21:48:15 +00:00
nakayama
3d642aeb5c Interrupt handlers are now allocated by kmem_zalloc(9), so free
them by kmem_free(9).
2016-05-13 21:24:11 +00:00
nakayama
4cb5a9c6dd Allocate interrupt handlers for clockintr and statintr dynamically. 2016-05-13 21:23:30 +00:00
nakayama
78ba29b05a Use newly introduced intrhand_alloc(). 2016-05-13 21:22:47 +00:00
palle
4b8507f0c9 Fixed typo in comment + reorder parameters for trap debug output to match function prototype for data_access_fault() 2016-05-13 21:21:43 +00:00
nakayama
948555d679 - ci_paddr is always 64-bit.
- intrlev is array of pointer.
- ih_ack is pointer.
2016-05-13 21:21:25 +00:00
maxv
b9750d0de9 Bring some amd64 swag. No functional changes. 2016-05-13 14:03:00 +00:00
christos
4b31d24b7f From scole_mail:
So here is a patch to get basic ski console output working.  The ski
simulator was decoding the wrong registers in ssccnputc() due to
automagically inlined ssc() which contains a "break" simulated system
call.

The ski loader "skiload" has almost exactly the same inline assembly
call for ssc(), but for whatever reason, (maybe ssc() and
ski_cons_putchar() are in different files?), the ssc() function didn't
get inlined and I/O worked fine.
2016-05-13 13:40:55 +00:00
maxv
d32d8095a7 KNF a little, use C-style comments, and remove susword/fusword. No
functional changes.
2016-05-13 13:24:01 +00:00
maxv
2b98d8b4ef Actually, make the NOX part amd64-specific. The secondary CPUs bug is not
yet fixed on i386.
2016-05-13 11:47:02 +00:00
maxv
5d4038a3e2 KNF, so it appears aligned on NXR. 2016-05-13 11:17:20 +00:00
maxv
d8433c925e Remap the rodata and data+bss segments with large pages on x86. There still
is a bug in the way the text segment is mapped, but I'll see later.
2016-05-13 10:24:42 +00:00
maxv
7c62ff1587 Define __kernel_end. 2016-05-13 10:18:01 +00:00
maxv
f1985d170d Xen therefore uses x86/db_memrw.c, as I suspected. Define __rodata_start
in the Xen ld scripts, so that it can compile. We put the __rodata_start
definition right before __data_start, for it to appear as dead code, since
the rodata segment is not yet mapped independently on Xen.
2016-05-13 05:45:13 +00:00
maxv
f4ea937e9d KNF, and reduce the diff between amd64 and i386. 2016-05-12 09:40:23 +00:00
maxv
64e6bd21bc Map the data+bss chunk independently on amd64, and remove the X
permission on it.
2016-05-12 09:05:16 +00:00
maxv
fd64ae1b5b Define fillkpt_nox, which sets up a set of pages and puts the NOX bit on
them by using nox_flag. Use fillkpt_nox to map the rodata segment
without X permissions.
2016-05-12 07:51:09 +00:00
maxv
a819d82371 Map the rodata segment independently on amd64, and remove the W permission
on it.
2016-05-12 07:21:18 +00:00
maxv
a23ebbfe56 KNF the Xen ld scripts on x86. 2016-05-12 06:57:55 +00:00
maxv
09b37bb062 Split the {text+rodata} chunk in two separate chunks on x86. The
rodata segment now loses the large page optimization, gets mapped inside
the data segment, and therefore becomes RWX. It may break the build on
Xen.
2016-05-12 06:45:16 +00:00
ozaki-r
040205ae93 Protect ifnet list with psz and psref
The change ensures that ifnet objects in the ifnet list aren't freed during
list iterations by using pserialize(9) and psref(9).

Note that the change adds a pslist(9) for ifnet but doesn't remove the
original ifnet list (ifnet_list) to avoid breaking kvm(3) users. We
shouldn't use the original list in the kernel anymore.
2016-05-12 02:24:16 +00:00
maxv
1527136e67 There is a bug in the way the secondary CPUs are launched on amd64.
When CPU0 is launched, EFER_NXE is enabled in it, and it allows it to
handle pages that have the NOX bit. When the secondary CPUs are
launched, however, EFER_NXE is enabled only after paging is set in their
%cr0. And therefore, between the moment when paging is enabled and the
moment when EFER_NXE is enabled, the secondary CPUs cannot access pages
that have the NOX bit - they crash if they try to.

The funny thing is that in order to enable EFER_NXE, the secondary CPUs
give a look at cpu_feature[2], which is in the DATA segment, which in
turn could have the NOX bit. In other words, the secondary CPUs crash if
the DATA segment is mapped with the NOX bit.

Fix this by enabling EFER_NXE in the secondary CPUs before enabling
paging. CPU0 initializes nox_flag to the 32bit version of PG_NX if NOX
is supported; the secondary CPUs then use nox_flag to know whether NOX
is supported.

nox_flag will be used for other purposes soon.
2016-05-11 19:35:08 +00:00
bouyer
ba413bf9c2 As proposed in
http://mail-index.netbsd.org/tech-kern/2016/04/28/msg020504.html
add gpio interrupt support to the gpio framework, and an implementation
for the allwinner gpio backend (tested on A20 only).
gpio(4) has new public functions:
- gpio_intr() called by backends when an interrupt condition for
  a gpio pin is present
- gpio_find_device() and gpio_get_name(), support functions for
  gpio(4) users, wich respectively returns a void * cookie for a gpio device
  given its name, and returns the name given the cookie.
- gpio_pin_ctl_intr(), which is used to configure interrupts on a gpio pin and
  registers a callback.
- gpio_pin_irqen(), which is used to mask/unmask interrupts on a pin.

Nothing in the NetBSD tree uses this yet, but I have a i2c driver
(at https://github.com/mbouyer/marine_chartplotter/tree/master/software/NetBSD/driver) which uses it.
2016-05-11 18:33:40 +00:00
maxv
9acd6328a2 Switch to C-style comments, and reduce a little the diff between i386 and
amd64. No functional changes.
2016-05-11 17:48:05 +00:00
riastradh
fc1fa2bfde Enable nouveau in i386/ALL. Omit incorrect option NV_DEBUG.
NV_DEBUG does not appear except as a macro function in nouveau, which
is broken by defining it on the command line.

From coypu.
2016-05-11 02:09:10 +00:00
palle
a86d6c4649 Update TODO: sun4v interrupts works (mostly) + note issue with mpt(4) on sun4v systems 2016-05-10 19:35:08 +00:00
palle
7820dc41e7 sun4v: make device interrupts work. Introduce a new intrhand_alloc() function for allocation of interrupt handlers and adapt to this. Parts from OpenBSD. ok martin@ 2016-05-10 19:23:59 +00:00
skrll
f92670f913 Use the MI usb majors 2016-05-09 15:23:23 +00:00