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3728 Commits

Author SHA1 Message Date
tsutsui
77addc8b55 Increase buffer size for s[dt]-targets PROM property 
otherwise some machines (including my SS1+) with old PROM fails to get it.
 2004-04-23 13:04:59 +00:00
hannken
82161a9cbe Protect against multiple inclusion. 2004-04-23 09:20:20 +00:00
pk
a2ce1a6818 ctx_free: reset the context's page table pointers in each context table. 2004-04-22 11:57:33 +00:00
pk
c996a0d95b Fix logic botch in previous commit. 2004-04-22 11:45:48 +00:00
pk
4c005fd35b Mostly undo rev. 1.287: for modified pages a table walk must be forced on 
the next write access to get the modified bit set in the PTE and that
won't happen if it hits the cache.
 2004-04-22 10:14:58 +00:00
pk
a22adee52d Default to not inlining __cpu_simple_lock(). 
- the locore version attempts to detect stuck locks
 - not inlining saves about 60K on the kernel's text
 2004-04-20 15:55:30 +00:00
pk
aa53aca844 Turn __CPU_SIMPLE_LOCK_INLINE into !__CPU_SIMPLE_LOCK_NOINLINE, so we don't 
screw up user land.
 2004-04-20 08:48:03 +00:00
pk
e2cab98f9e Always provide the __cpu_simple_lock() entry point (for LKMs). 2004-04-20 08:38:41 +00:00
pk
ce78973db2 Provide a fast trap path for AST IPIs. 2004-04-20 08:36:46 +00:00
pk
3097bbf440 pmap_extract4m: We can read a spurious invalid pte if the system is in 
the middle of the PTE update protocol. So, if at first we get an invalid
PTE, retry with the demap lock held.
 2004-04-19 15:20:42 +00:00
pk
2e643fb9ae __cpu_simple_lock() isn't a pure function. 2004-04-19 12:41:53 +00:00
pk
a484ad4f3f CMP_PTE_USER_READ4M: drop instruction that's effectively a no-op. 2004-04-19 10:01:41 +00:00
pk
fecb3b619b Drop spurious variable. 2004-04-19 08:50:21 +00:00
pk
03a07196d9 srmmu_vcache_flush_page/range: cover the case where we're called during 
bootstrap before the cache parameters are setup.
 2004-04-18 21:49:09 +00:00
pk
27f928584a Code srmmu_vcache_flush_range & srmmu_vcache_flush_page more efficiently. 2004-04-18 20:46:39 +00:00
pk
57bbd955d1 Various ft_srmmu_vcache_*() functions: use `branch on greater (unsigned)' 
instead of `branch on positive'.
 2004-04-18 20:44:39 +00:00
pk
68f30ee7af Make inlining __cpu_simple_lock() optional. Add a version with a built-in 
spin out counter that panics with a diagnostic.
 2004-04-18 19:20:09 +00:00
pk
38bdc6fab2 Remove the cache_flush() trampoline; it's no longer directly cross-called. 
Instead, implement the MP parts in terms of cross-callable vcache_flush_range()
function.
 2004-04-17 23:45:40 +00:00
pk
66a6704d83 Update fast xcall interrupt event counter. 
ft_srmmu_vcache_flush_range: adjust length for address alignment
 2004-04-17 23:28:44 +00:00
pk
e68993f7e4 Add EV_COUNT. 2004-04-17 22:36:54 +00:00
pk
3c3af40e65 Add xcall event counters. 2004-04-17 22:34:14 +00:00
pk
89f5c8768c When acknowledging a sun4m soft interrupt, read back the pending interrupts 
hw register to make sure it gets through on Ross CPUs.
 2004-04-17 11:55:06 +00:00
pk
1e5ff8a716 raise_ipi: don't bother fetching the cpu type from memory in order to 
avoid one instruction.
 2004-04-17 11:50:23 +00:00
pk
727a9ca138 The macro CMP_PTE_USER_READ4M now needs to consider more PTE access 
rights combinations, since the access rights table in pmap has changed.
 2004-04-17 11:26:36 +00:00
pk
66178209d2 Use fast cross calls for MP cache flush ops. 2004-04-17 10:13:13 +00:00
pk
f714ca590d Add CPUINFO_XMSG_* symbols for use in fast xcall handlers. 2004-04-17 10:07:58 +00:00
pk
ebfb6e3b0a Implement fast trap handlers for TLB and cache flushes. 2004-04-17 10:06:29 +00:00
pk
901271fbc8 Use a fast cross call for TLB flushes. 2004-04-17 10:04:20 +00:00
pk
4eac0385f6 xcallintr: arg3 is gone. 2004-04-17 10:01:55 +00:00
pk
8bc2760490 Add support for fast cross call handlers that execute in the trap window 
on the destination CPU. The `fast handler' address takes the place of the
unused fourth argument to xcall().
 2004-04-17 10:01:11 +00:00
pk
299dfa38bf De-__P(). 2004-04-15 10:07:32 +00:00
pk
dab35b2e8d xcall: increase spin-out; fix diag output. 2004-04-15 08:11:20 +00:00
pk
cd891bd771 Re-enable the HyperSPARC on-board instruction cache on multi-processor machines. 2004-04-13 14:55:48 +00:00
pk
86fce030ee Handle `unimplemented flush' traps by flushing the entire I-cache (if 
there is one).
 2004-04-13 14:04:29 +00:00
pk
e76253f84e Turn FLUSH instructions that wind up here into no-ops. 2004-04-13 14:00:24 +00:00
pk
ebfcdb612b Drop the special sun4d `tlb flush' lock. The pte update function already 
serialises access to the PTEs to reliably get ref/mod bits.

Rename pte4m_lock => demap_lock.
 2004-04-12 14:26:01 +00:00
pk
4f969ab39c pv_syncflags4m: no need to flush the cache. If the page is still mapped, 
its ref/mod status may change at any moment anyway. If a definitive status
is required the UVM code will unmap the page first.
 2004-04-12 12:52:42 +00:00
pk
fd1ba25dd1 Drop sparc_protection_init4m() in favour of a (ro) data initialiser. 2004-04-12 10:00:28 +00:00
pk
9450998e71 pmap_copy_page4m(): we only need to flush the local cache since we use 
private virtual addresses.
 2004-04-10 20:51:24 +00:00
pk
9d95da7f96 Remove a number of redundant TLB page flushed, which are now done in 
setpgt4m_va() and updatepte4m() as necessary.
 2004-04-10 20:43:02 +00:00
pk
6452e19758 De-__P(). 2004-04-10 20:00:29 +00:00
pk
217297d742 Remove a remnant instance of __P(). 2004-04-10 19:58:45 +00:00
pk
6d82d89741 Expose CPUSET_ALL to non-MULTIPROCESSOR source. 2004-04-10 19:55:57 +00:00
pk
667d14673b Group updatepte4m() and the MP & SP versions of setpgt4m_va() together, 
which is just a bit more pleasing to the eyes.
 2004-04-10 19:40:19 +00:00
pk
83037215bf Do not maintain the number of valid pages per segment (`sg_npte') anymore 
for the kernel map on SRMMU machines. This allows pmap_kenter() and
pmap_kremove() to update mappings without needing to lock the pmap
or raising the interrupt level.
 2004-04-10 19:22:59 +00:00
pk
2648b0d48c pmap_protect4m: skip PTE update for invalid pages in the specified range. 2004-04-10 18:48:35 +00:00
pk
f852e1c1e4 setpte4m: remove ineffective debug assertions. 2004-04-10 18:40:04 +00:00
fair
e2b036a2e4 Add comment to indicate that the SunSwift Sbus HME/FAS366 SCSI 
combination board attaches esp* at sbus*; it's not just "older proms"
 2004-04-10 04:02:29 +00:00
pk
f95fd4f56f compat mode: skip double map at VA 0 if the physical load address is 0. 
This allows a much wider range of historic kernels to be booted (w/ `-C').
 2004-04-08 07:35:34 +00:00
pk
12d5178857 For now, disable Hypersparc instruction cache on MP machines. 2004-04-04 18:54:01 +00:00