Remove the cache_flush() trampoline; it's no longer directly cross-called.
Instead, implement the MP parts in terms of cross-callable vcache_flush_range() function.
This commit is contained in:
pk
parent
35b9f3ec72
commit
38bdc6fab2
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.h,v 1.66 2004/01/04 11:33:31 jdolecek Exp $ */
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/* $NetBSD: cpu.h,v 1.67 2004/04/17 23:45:40 pk Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -218,8 +218,6 @@ void zs_kgdb_init(void);
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#endif
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/* fb.c */
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void fb_unblank(void);
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/* cache.c */
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void cache_flush(caddr_t, u_int);
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/* kgdb_stub.c */
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#ifdef KGDB
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void kgdb_attach(int (*)(void *), void (*)(void *, int), void *);
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@ -1,4 +1,4 @@
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/* $NetBSD: cache.c,v 1.85 2004/04/17 10:13:13 pk Exp $ */
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/* $NetBSD: cache.c,v 1.86 2004/04/17 23:45:40 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -59,7 +59,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.85 2004/04/17 10:13:13 pk Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.86 2004/04/17 23:45:40 pk Exp $");
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#include "opt_multiprocessor.h"
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#include "opt_sparc_arch.h"
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@ -339,15 +339,6 @@ turbosparc_cache_enable()
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#endif /* SUN4M || SUN4D */
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/* XXX - should inline */
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void
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cache_flush(base, len)
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caddr_t base;
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u_int len;
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{
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cpuinfo.cache_flush(base, len, getcontext());
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}
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/*
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* Note: the sun4 & sun4c the cache flush functions ignore the `ctx'
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* parameter. This can be done since the pmap operations that need
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@ -503,10 +494,9 @@ sun4_vcache_flush_page_hw(va, ctx)
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#define CACHE_FLUSH_MAGIC (CACHEINFO.c_totalsize / PAGE_SIZE)
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void
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sun4_cache_flush(base, len, ctx)
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sun4_cache_flush(base, len)
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caddr_t base;
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u_int len;
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int ctx;
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{
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int i, ls, baseoff;
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char *p;
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@ -540,7 +530,7 @@ sun4_cache_flush(base, len, ctx)
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cachestats.cs_ra[min(i, MAXCACHERANGE)]++;
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#endif
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if (i < CACHE_FLUSH_MAGIC) {
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if (__predict_true(i < CACHE_FLUSH_MAGIC)) {
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/* cache_flush_page, for i pages */
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p = (char *)((int)base & ~baseoff);
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if (CACHEINFO.c_hwflush) {
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@ -557,19 +547,20 @@ sun4_cache_flush(base, len, ctx)
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baseoff = (u_int)base & SGOFSET;
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i = (baseoff + len + SGOFSET) >> SGSHIFT;
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if (i == 1)
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sun4_vcache_flush_segment(VA_VREG(base), VA_VSEG(base), ctx);
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else {
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if (HASSUN4_MMU3L) {
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baseoff = (u_int)base & RGOFSET;
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i = (baseoff + len + RGOFSET) >> RGSHIFT;
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if (i == 1)
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sun4_vcache_flush_region(VA_VREG(base), ctx);
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else
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sun4_vcache_flush_context(ctx);
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} else
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sun4_vcache_flush_context(ctx);
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if (__predict_true(i == 1)) {
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sun4_vcache_flush_segment(VA_VREG(base), VA_VSEG(base), 0);
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return;
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}
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if (HASSUN4_MMU3L) {
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baseoff = (u_int)base & RGOFSET;
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i = (baseoff + len + RGOFSET) >> RGSHIFT;
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if (i == 1)
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sun4_vcache_flush_region(VA_VREG(base), 0);
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else
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sun4_vcache_flush_context(0);
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} else
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sun4_vcache_flush_context(0);
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}
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@ -694,7 +685,7 @@ srmmu_vcache_flush_page(va, ctx)
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* functions will not always cross flush it in the MP case (because
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* may not be active on this CPU) we flush the TLB entry now.
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*/
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if (cpuinfo.cpu_type == CPUTYP_HS_MBUS)
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/*if (cpuinfo.cpu_type == CPUTYP_HS_MBUS) -- more work than it's worth */
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sta(va | ASI_SRMMUFP_L3, ASI_SRMMUFP, 0);
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#endif
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@ -711,56 +702,60 @@ srmmu_cache_flush_all()
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srmmu_vcache_flush_context(0);
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}
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void
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srmmu_vcache_flush_range(int va, int len, int ctx)
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{
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int i, ls, offset;
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char *p;
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int octx;
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/* Compute # of cache lines covered by this range */
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ls = CACHEINFO.c_linesize;
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offset = va & (ls - 1);
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i = (offset + len + ls - 1) >> CACHEINFO.c_l2linesize;
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p = (char *)(va & -ls);
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octx = getcontext4m();
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trapoff();
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setcontext4m(ctx);
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for (; --i >= 0; p += ls)
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sta(p, ASI_IDCACHELFP, 0);
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#if defined(MULTIPROCESSOR)
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if (cpuinfo.cpu_type == CPUTYP_HS_MBUS) {
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/*
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* See hypersparc comment in srmmu_vcache_flush_page().
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*/
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offset = va & PGOFSET;
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i = (offset + len + PGOFSET) >> PGSHIFT;
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va = va & ~PGOFSET;
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for (; --i >= 0; va += PAGE_SIZE)
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sta(va | ASI_SRMMUFP_L3, ASI_SRMMUFP, 0);
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}
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#endif
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setcontext4m(octx);
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trapon();
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return;
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}
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/*
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* Flush a range of virtual addresses (in the current context).
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* The first byte is at (base&~PGOFSET) and the last one is just
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* before byte (base+len).
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*
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* We choose the best of (context,segment,page) here.
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*/
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#define CACHE_FLUSH_MAGIC (CACHEINFO.c_totalsize / PAGE_SIZE)
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void
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srmmu_cache_flush(base, len, ctx)
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srmmu_cache_flush(base, len)
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caddr_t base;
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u_int len;
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int ctx;
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{
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int i, ls, baseoff;
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char *p;
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int ctx = getcontext4m();
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int i, baseoff;
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if (len < PAGE_SIZE) {
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int octx;
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/* less than a page, flush just the covered cache lines */
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ls = CACHEINFO.c_linesize;
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baseoff = (int)base & (ls - 1);
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i = (baseoff + len + ls - 1) >> CACHEINFO.c_l2linesize;
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p = (char *)((int)base & -ls);
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octx = getcontext4m();
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trapoff();
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setcontext4m(ctx);
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for (; --i >= 0; p += ls)
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sta(p, ASI_IDCACHELFP, 0);
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#if defined(MULTIPROCESSOR)
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if (cpuinfo.cpu_type == CPUTYP_HS_MBUS) {
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/*
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* See hypersparc comment in srmmu_vcache_flush_page().
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* Just flush both possibly touched pages
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* from the TLB.
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*/
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int va = (int)base & ~0xfff;
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sta(va | ASI_SRMMUFP_L3, ASI_SRMMUFP, 0);
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sta((va+4096) | ASI_SRMMUFP_L3, ASI_SRMMUFP, 0);
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}
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#endif
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setcontext4m(octx);
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trapon();
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return;
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}
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/*
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* Figure out how much must be flushed.
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* Figure out the most efficient way to flush.
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*
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* If we need to do CACHE_FLUSH_MAGIC pages, we can do a segment
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* in the same number of loop iterations. We can also do the whole
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@ -775,62 +770,54 @@ srmmu_cache_flush(base, len, ctx)
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* segments), but I did not want to debug that now and it is
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* not clear it would help much.
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*
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* (XXX the magic number 16 is now wrong, must review policy)
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*/
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baseoff = (int)base & PGOFSET;
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i = (baseoff + len + PGOFSET) >> PGSHIFT;
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cachestats.cs_nraflush++;
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#ifdef notyet
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cachestats.cs_ra[min(i, MAXCACHERANGE)]++;
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#endif
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if (i < CACHE_FLUSH_MAGIC) {
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int octx;
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/* cache_flush_page, for i pages */
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p = (char *)((int)base & ~baseoff);
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ls = CACHEINFO.c_linesize;
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i <<= PGSHIFT - CACHEINFO.c_l2linesize;
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octx = getcontext4m();
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trapoff();
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setcontext4m(ctx);
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for (; --i >= 0; p += ls)
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sta(p, ASI_IDCACHELFP, 0);
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if (__predict_true(len < CACHEINFO.c_totalsize)) {
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#if defined(MULTIPROCESSOR)
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if (cpuinfo.cpu_type == CPUTYP_HS_MBUS) {
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/* Just flush the segment(s) from the TLB */
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/* XXX - assumes CACHE_FLUSH_MAGIC <= NBPSG */
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int va = (int)base & ~SGOFSET;
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sta(va | ASI_SRMMUFP_L2, ASI_SRMMUFP, 0);
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sta((va+NBPSG) | ASI_SRMMUFP_L2, ASI_SRMMUFP, 0);
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}
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FXCALL3(cpuinfo.sp_vcache_flush_range,
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cpuinfo.ft_vcache_flush_range,
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(int)base, len, ctx, CPUSET_ALL);
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#else
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cpuinfo.sp_vcache_flush_range((int)base, len, ctx);
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#endif
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setcontext4m(octx);
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trapon();
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return;
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}
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cachestats.cs_nraflush++;
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baseoff = (u_int)base & SGOFSET;
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i = (baseoff + len + SGOFSET) >> SGSHIFT;
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if (i == 1)
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if (__predict_true(i == 1)) {
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#if defined(MULTIPROCESSOR)
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FXCALL3(cpuinfo.sp_vcache_flush_segment,
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cpuinfo.ft_vcache_flush_segment,
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VA_VREG(base), VA_VSEG(base), ctx, CPUSET_ALL);
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#else
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srmmu_vcache_flush_segment(VA_VREG(base), VA_VSEG(base), ctx);
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else {
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baseoff = (u_int)base & RGOFSET;
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i = (baseoff + len + RGOFSET) >> RGSHIFT;
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p = (char *)VA_VREG(base);
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while (i--) {
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srmmu_vcache_flush_region((int)p, ctx);
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p += NBPRG;
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}
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#endif
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return;
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}
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baseoff = (u_int)base & RGOFSET;
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i = (baseoff + len + RGOFSET) >> RGSHIFT;
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while (i--) {
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#if defined(MULTIPROCESSOR)
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FXCALL2(cpuinfo.sp_vcache_flush_region,
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cpuinfo.ft_vcache_flush_region,
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VA_VREG(base), ctx, CPUSET_ALL);
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#else
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srmmu_vcache_flush_region(VA_VREG(base), ctx);
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#endif
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base += NBPRG;
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}
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}
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int ms1_cacheflush_magic = 0;
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#define MS1_CACHEFLUSH_MAGIC ms1_cacheflush_magic
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void
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ms1_cache_flush(base, len, ctx)
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ms1_cache_flush(base, len)
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caddr_t base;
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u_int len;
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int ctx;
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{
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/*
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* Although physically tagged, we still need to flush the
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@ -924,10 +911,9 @@ cypress_cache_flush_all()
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void
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viking_cache_flush(base, len, ctx)
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viking_cache_flush(base, len)
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caddr_t base;
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u_int len;
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int ctx;
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{
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}
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@ -1078,14 +1064,4 @@ smp_vcache_flush_context(ctx)
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FXCALL1(cpuinfo.sp_vcache_flush_context, cpuinfo.ft_vcache_flush_context,
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ctx, CPUSET_ALL);
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}
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void
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smp_cache_flush(va, size, ctx)
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caddr_t va;
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u_int size;
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int ctx;
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{
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XCALL3(cpuinfo.sp_cache_flush, va, size, ctx, CPUSET_ALL);
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}
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#endif /* MULTIPROCESSOR */
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@ -1,4 +1,4 @@
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/* $NetBSD: cache.h,v 1.30 2004/04/17 10:13:13 pk Exp $ */
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/* $NetBSD: cache.h,v 1.31 2004/04/17 23:45:40 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -169,13 +169,14 @@ void sun4_vcache_flush_region(int, int); /* flush region in cur ctx */
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void sun4_vcache_flush_segment(int, int, int);/* flush seg in cur ctx */
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void sun4_vcache_flush_page(int va, int); /* flush page in cur ctx */
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void sun4_vcache_flush_page_hw(int va, int); /* flush page in cur ctx */
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void sun4_cache_flush(caddr_t, u_int, int); /* flush region */
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void sun4_cache_flush(caddr_t, u_int); /* flush range */
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void srmmu_vcache_flush_context(int); /* flush current context */
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void srmmu_vcache_flush_region(int, int); /* flush region in cur ctx */
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void srmmu_vcache_flush_segment(int, int, int);/* flush seg in cur ctx */
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void srmmu_vcache_flush_page(int va, int); /* flush page in cur ctx */
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void srmmu_cache_flush(caddr_t, u_int, int); /* flush region */
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void srmmu_vcache_flush_range(int, int, int);
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void srmmu_cache_flush(caddr_t, u_int); /* flush range */
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/* `Fast trap' versions for use in cross-call cache flushes on MP systems */
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#if defined(MULTIPROCESSOR)
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@ -183,15 +184,17 @@ void ft_srmmu_vcache_flush_context(int); /* flush current context */
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void ft_srmmu_vcache_flush_region(int, int); /* flush region in cur ctx */
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void ft_srmmu_vcache_flush_segment(int, int, int);/* flush seg in cur ctx */
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void ft_srmmu_vcache_flush_page(int va, int);/* flush page in cur ctx */
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void ft_srmmu_vcache_flush_range(int, int, int);/* flush range in cur ctx */
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#else
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#define ft_srmmu_vcache_flush_context 0
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#define ft_srmmu_vcache_flush_region 0
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#define ft_srmmu_vcache_flush_segment 0
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#define ft_srmmu_vcache_flush_page 0
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#define ft_srmmu_vcache_flush_range 0
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#endif /* MULTIPROCESSOR */
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void ms1_cache_flush(caddr_t, u_int, int);
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void viking_cache_flush(caddr_t, u_int, int);
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void ms1_cache_flush(caddr_t, u_int);
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void viking_cache_flush(caddr_t, u_int);
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void viking_pcache_flush_page(paddr_t, int);
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void srmmu_pcache_flush_line(int, int);
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void hypersparc_pure_vcache_flush(void);
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@ -207,7 +210,8 @@ extern void sparc_noop(void);
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#define noop_vcache_flush_region (void (*)(int,int))sparc_noop
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#define noop_vcache_flush_segment (void (*)(int,int,int))sparc_noop
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#define noop_vcache_flush_page (void (*)(int,int))sparc_noop
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#define noop_cache_flush (void (*)(caddr_t,u_int,int))sparc_noop
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#define noop_vcache_flush_range (void (*)(int,int,int))sparc_noop
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#define noop_cache_flush (void (*)(caddr_t,u_int))sparc_noop
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#define noop_pcache_flush_page (void (*)(paddr_t,int))sparc_noop
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#define noop_pure_vcache_flush (void (*)(void))sparc_noop
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#define noop_cache_flush_all (void (*)(void))sparc_noop
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@ -220,13 +224,13 @@ void smp_vcache_flush_context(int); /* flush current context */
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void smp_vcache_flush_region(int,int); /* flush region in cur ctx */
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void smp_vcache_flush_segment(int, int, int);/* flush seg in cur ctx */
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void smp_vcache_flush_page(int va,int); /* flush page in cur ctx */
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void smp_cache_flush(caddr_t, u_int, int); /* flush region */
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#define cache_flush_page(va,ctx) cpuinfo.vcache_flush_page(va,ctx)
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#define cache_flush_segment(vr,vs,ctx) cpuinfo.vcache_flush_segment(vr,vs,ctx)
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#define cache_flush_region(vr,ctx) cpuinfo.vcache_flush_region(vr,ctx)
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#define cache_flush_context(ctx) cpuinfo.vcache_flush_context(ctx)
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#define cache_flush(va,len) cpuinfo.cache_flush(va,len)
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#define pcache_flush_page(pa,flag) cpuinfo.pcache_flush_page(pa,flag)
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.c,v 1.184 2004/04/17 10:01:11 pk Exp $ */
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/* $NetBSD: cpu.c,v 1.185 2004/04/17 23:45:40 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -52,7 +52,7 @@
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*/
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#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.184 2004/04/17 10:01:11 pk Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.185 2004/04/17 23:45:40 pk Exp $");
|
||||
|
||||
#include "opt_multiprocessor.h"
|
||||
#include "opt_lockdebug.h"
|
||||
|
|
@ -529,7 +529,6 @@ cpu_attach(struct cpu_softc *sc, int node, int mid)
|
|||
continue;
|
||||
#define SET_CACHE_FUNC(x) \
|
||||
if (cpi->x != __CONCAT(noop_,x)) cpi->x = __CONCAT(smp_,x)
|
||||
SET_CACHE_FUNC(cache_flush);
|
||||
SET_CACHE_FUNC(vcache_flush_page);
|
||||
SET_CACHE_FUNC(vcache_flush_segment);
|
||||
SET_CACHE_FUNC(vcache_flush_region);
|
||||
|
|
@ -1061,6 +1060,7 @@ struct module_info module_sun4 = {
|
|||
sun4_vcache_flush_segment, NULL,
|
||||
sun4_vcache_flush_region, NULL,
|
||||
sun4_vcache_flush_context, NULL,
|
||||
NULL, NULL,
|
||||
noop_pcache_flush_page,
|
||||
noop_pure_vcache_flush,
|
||||
noop_cache_flush_all,
|
||||
|
|
@ -1087,7 +1087,7 @@ getcacheinfo_sun4(sc, node)
|
|||
ci->c_nlines = 0;
|
||||
|
||||
/* Override cache flush functions */
|
||||
sc->sp_cache_flush = noop_cache_flush;
|
||||
sc->cache_flush = noop_cache_flush;
|
||||
sc->sp_vcache_flush_page = noop_vcache_flush_page;
|
||||
sc->sp_vcache_flush_segment = noop_vcache_flush_segment;
|
||||
sc->sp_vcache_flush_region = noop_vcache_flush_region;
|
||||
|
|
@ -1186,6 +1186,7 @@ struct module_info module_sun4c = {
|
|||
sun4_vcache_flush_segment, NULL,
|
||||
sun4_vcache_flush_region, NULL,
|
||||
sun4_vcache_flush_context, NULL,
|
||||
NULL, NULL,
|
||||
noop_pcache_flush_page,
|
||||
noop_pure_vcache_flush,
|
||||
noop_cache_flush_all,
|
||||
|
|
@ -1393,6 +1394,7 @@ struct module_info module_ms1 = {
|
|||
noop_vcache_flush_segment, NULL,
|
||||
noop_vcache_flush_region, NULL,
|
||||
noop_vcache_flush_context, NULL,
|
||||
noop_vcache_flush_range, NULL,
|
||||
noop_pcache_flush_page,
|
||||
noop_pure_vcache_flush,
|
||||
ms1_cache_flush_all,
|
||||
|
|
@ -1438,6 +1440,7 @@ struct module_info module_ms2 = { /* UNTESTED */
|
|||
srmmu_vcache_flush_segment, NULL,
|
||||
srmmu_vcache_flush_region, NULL,
|
||||
srmmu_vcache_flush_context, NULL,
|
||||
srmmu_vcache_flush_range, NULL,
|
||||
noop_pcache_flush_page,
|
||||
noop_pure_vcache_flush,
|
||||
srmmu_cache_flush_all,
|
||||
|
|
@ -1464,6 +1467,7 @@ struct module_info module_swift = {
|
|||
srmmu_vcache_flush_segment, NULL,
|
||||
srmmu_vcache_flush_region, NULL,
|
||||
srmmu_vcache_flush_context, NULL,
|
||||
srmmu_vcache_flush_range, NULL,
|
||||
noop_pcache_flush_page,
|
||||
noop_pure_vcache_flush,
|
||||
srmmu_cache_flush_all,
|
||||
|
|
@ -1507,6 +1511,7 @@ struct module_info module_hypersparc = {
|
|||
srmmu_vcache_flush_segment, ft_srmmu_vcache_flush_segment,
|
||||
srmmu_vcache_flush_region, ft_srmmu_vcache_flush_region,
|
||||
srmmu_vcache_flush_context, ft_srmmu_vcache_flush_context,
|
||||
srmmu_vcache_flush_range, ft_srmmu_vcache_flush_range,
|
||||
noop_pcache_flush_page,
|
||||
hypersparc_pure_vcache_flush,
|
||||
hypersparc_cache_flush_all,
|
||||
|
|
@ -1573,6 +1578,7 @@ struct module_info module_cypress = {
|
|||
srmmu_vcache_flush_segment, ft_srmmu_vcache_flush_segment,
|
||||
srmmu_vcache_flush_region, ft_srmmu_vcache_flush_region,
|
||||
srmmu_vcache_flush_context, ft_srmmu_vcache_flush_context,
|
||||
srmmu_vcache_flush_range, ft_srmmu_vcache_flush_range,
|
||||
noop_pcache_flush_page,
|
||||
noop_pure_vcache_flush,
|
||||
cypress_cache_flush_all,
|
||||
|
|
@ -1600,6 +1606,7 @@ struct module_info module_turbosparc = {
|
|||
srmmu_vcache_flush_segment, NULL,
|
||||
srmmu_vcache_flush_region, NULL,
|
||||
srmmu_vcache_flush_context, NULL,
|
||||
srmmu_vcache_flush_range, NULL,
|
||||
noop_pcache_flush_page,
|
||||
noop_pure_vcache_flush,
|
||||
srmmu_cache_flush_all,
|
||||
|
|
@ -1635,7 +1642,7 @@ cpumatch_turbosparc(sc, mp, node)
|
|||
sc->mmu_enable = 0;
|
||||
sc->cache_enable = 0;
|
||||
sc->get_syncflt = 0;
|
||||
sc->sp_cache_flush = 0;
|
||||
sc->cache_flush = 0;
|
||||
sc->sp_vcache_flush_page = 0;
|
||||
sc->sp_vcache_flush_segment = 0;
|
||||
sc->sp_vcache_flush_region = 0;
|
||||
|
|
@ -1677,6 +1684,7 @@ struct module_info module_viking = {
|
|||
noop_vcache_flush_segment, NULL,
|
||||
noop_vcache_flush_region, NULL,
|
||||
noop_vcache_flush_context, NULL,
|
||||
noop_vcache_flush_range, NULL,
|
||||
viking_pcache_flush_page,
|
||||
noop_pure_vcache_flush,
|
||||
noop_cache_flush_all,
|
||||
|
|
@ -1872,6 +1880,7 @@ struct module_info module_viking_sun4d = {
|
|||
noop_vcache_flush_segment, NULL,
|
||||
noop_vcache_flush_region, NULL,
|
||||
noop_vcache_flush_context, NULL,
|
||||
noop_vcache_flush_range, NULL,
|
||||
viking_pcache_flush_page,
|
||||
noop_pure_vcache_flush,
|
||||
noop_cache_flush_all,
|
||||
|
|
@ -2048,15 +2057,17 @@ getcpuinfo(sc, node)
|
|||
MPCOPY(cache_enable);
|
||||
MPCOPY(get_syncflt);
|
||||
MPCOPY(get_asyncflt);
|
||||
MPCOPY(sp_cache_flush);
|
||||
MPCOPY(cache_flush);
|
||||
MPCOPY(sp_vcache_flush_page);
|
||||
MPCOPY(sp_vcache_flush_segment);
|
||||
MPCOPY(sp_vcache_flush_region);
|
||||
MPCOPY(sp_vcache_flush_context);
|
||||
MPCOPY(sp_vcache_flush_range);
|
||||
MPCOPY(ft_vcache_flush_page);
|
||||
MPCOPY(ft_vcache_flush_segment);
|
||||
MPCOPY(ft_vcache_flush_region);
|
||||
MPCOPY(ft_vcache_flush_context);
|
||||
MPCOPY(ft_vcache_flush_range);
|
||||
MPCOPY(pcache_flush_page);
|
||||
MPCOPY(pure_vcache_flush);
|
||||
MPCOPY(cache_flush_all);
|
||||
|
|
@ -2068,7 +2079,6 @@ getcpuinfo(sc, node)
|
|||
* Use the single-processor cache flush functions until
|
||||
* all CPUs are initialized.
|
||||
*/
|
||||
sc->cache_flush = sc->sp_cache_flush;
|
||||
sc->vcache_flush_page = sc->sp_vcache_flush_page;
|
||||
sc->vcache_flush_segment = sc->sp_vcache_flush_segment;
|
||||
sc->vcache_flush_region = sc->sp_vcache_flush_region;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: cpuvar.h,v 1.61 2004/04/17 11:50:23 pk Exp $ */
|
||||
/* $NetBSD: cpuvar.h,v 1.62 2004/04/17 23:45:40 pk Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1996 The NetBSD Foundation, Inc.
|
||||
|
|
@ -75,7 +75,7 @@ struct module_info {
|
|||
|
||||
void (*get_syncflt)(void);
|
||||
int (*get_asyncflt)(u_int *, u_int *);
|
||||
void (*sp_cache_flush)(caddr_t, u_int, int);
|
||||
void (*cache_flush)(caddr_t, u_int);
|
||||
void (*sp_vcache_flush_page)(int, int);
|
||||
void (*ft_vcache_flush_page)(int, int);
|
||||
void (*sp_vcache_flush_segment)(int, int, int);
|
||||
|
|
@ -84,6 +84,8 @@ struct module_info {
|
|||
void (*ft_vcache_flush_region)(int, int);
|
||||
void (*sp_vcache_flush_context)(int);
|
||||
void (*ft_vcache_flush_context)(int);
|
||||
void (*sp_vcache_flush_range)(int, int, int);
|
||||
void (*ft_vcache_flush_range)(int, int, int);
|
||||
void (*pcache_flush_page)(paddr_t, int);
|
||||
void (*pure_vcache_flush)(void);
|
||||
void (*cache_flush_all)(void);
|
||||
|
|
@ -230,8 +232,7 @@ struct cpu_info {
|
|||
* all processor modules.
|
||||
* The `ft_' versions are fast trap cache flush handlers.
|
||||
*/
|
||||
void (*cache_flush)(caddr_t, u_int, int);
|
||||
void (*sp_cache_flush)(caddr_t, u_int, int);
|
||||
void (*cache_flush)(caddr_t, u_int);
|
||||
void (*vcache_flush_page)(int, int);
|
||||
void (*sp_vcache_flush_page)(int, int);
|
||||
void (*ft_vcache_flush_page)(int, int);
|
||||
|
|
@ -245,6 +246,10 @@ struct cpu_info {
|
|||
void (*sp_vcache_flush_context)(int);
|
||||
void (*ft_vcache_flush_context)(int);
|
||||
|
||||
/* The are helpers for (*cache_flush)() */
|
||||
void (*sp_vcache_flush_range)(int, int, int);
|
||||
void (*ft_vcache_flush_range)(int, int, int);
|
||||
|
||||
void (*pcache_flush_page)(paddr_t, int);
|
||||
void (*pure_vcache_flush)(void);
|
||||
void (*cache_flush_all)(void);
|
||||
|
|
|
|||
Loading…
Reference in New Issue