don't matter in usespace.
Update list of intel family 6 model names (all current cpus) to include
everything upto and including sandy bridge and ivy bridge.
My i7 is no longer reported as a random P II.
family' and 'extended model' bits are used to create larger values
than the original 16bit value allowed for.
Calculate and save these values 'up-front' and use them throughout.
Untangle the (backwards) nested switch statement for amd 'model 15' cpus.
Works as badly as ever on my i7.
into global data.
Fix a stack alignment fubar that would cause a crash on a cirix 486.
Refactor identify code to common setup for normal identify and ucode
identify - which was missing a memset().
Contrary to the AMD implementation, it doesn't use xcalls to distribute
the update to all CPUs but relies on cpuctl(8) to bind itself to the
right CPU -- to keep it simple and avoid possible problems with
hyperthreading.
Also, it doesn't parse the vendor supplied file to pick the right
part for the present CPU model but relies on userland to prepare
files with specific filenames. I'll commit a pkg for this in a minute
(pkgsrc/sysutils/intel-microcode).
The ioctl interface changed; compatibility is provided (should be
limited to COMPAT_NETBSD6 as soon as this is available).
Implemented and enabled via CPU_UCODE kernel config option
for x86 and Xen Dom0.
Tested on different AMD machines with different
CPU families.
ok wiz@ for the manpages
ok releng@
ok core@ via releng@
allows us to properly identify new Intel 45nm processors, Core i7,
Atom, and the 45nm Xeon MP.
2. Properly decode several new Intel cache descriptors, as listed in the
most recent (March 2009) edition of Intel's Application Note 485.
3. Convert decode of the various features masks to use the newly added
snprintb_m(3) routine.
Addresses my PR bin/41289
Addresses my PR bin/41290
- Add interrupt shielding (direct hardware interrupts away from the
specified CPUs). Not documented just yet but will be soon.
- Redo /dev/cpu time_t compat so no kernel changes are needed.
x86:
- Make intr_establish, intr_disestablish safe to use when !cold.
- Distribute hardware interrupts among the CPUs, instead of directing
everything to the boot CPU.
- Add MD code for interrupt sheilding. This works in most cases but there is
a bug where delivery is not accepted by an LAPIC after redistribution. It
also needs re-balancing to make things fair after interrupts are turned
back on for a CPU.
so that it can return 128KB, 256KB and 512KB properly instead of
truncated 0MB or rounded 1MB.
Problem reported by nisimura@ on port-amd64 and port-i386.
flags from CPUID 80000001_EDX. Instead, keep the extended flags
separate, in ci_feature3_flags (Intel processors already kept a
separate ci_feature3_flag value).
2. Decode/display ci_feature3_flag in a vendor-specific manner, since
the definitions are vendor-specific.
OK cegger@
