The Intel and AMD docs (more or less) agree on how the cpuid 'extended
family' and 'extended model' bits are used to create larger values than the original 16bit value allowed for. Calculate and save these values 'up-front' and use them throughout. Untangle the (backwards) nested switch statement for amd 'model 15' cpus. Works as badly as ever on my i7.
This commit is contained in:
dsl
parent
74dad3229c
commit
cbb941ff11
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@ -1,4 +1,4 @@
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/* $NetBSD: i386.c,v 1.35 2013/01/05 16:38:12 dsl Exp $ */
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/* $NetBSD: i386.c,v 1.36 2013/01/05 21:16:22 dsl Exp $ */
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/*-
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* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
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@ -57,7 +57,7 @@
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#include <sys/cdefs.h>
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#ifndef lint
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__RCSID("$NetBSD: i386.c,v 1.35 2013/01/05 16:38:12 dsl Exp $");
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__RCSID("$NetBSD: i386.c,v 1.36 2013/01/05 21:16:22 dsl Exp $");
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#endif /* not lint */
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#include <sys/types.h>
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@ -95,6 +95,8 @@ struct cpu_info {
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int32_t ci_cpu_type; /* for cpu's without cpuid */
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int32_t ci_cpuid_level; /* highest cpuid supported */
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uint32_t ci_signature; /* X86 cpuid type */
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uint32_t ci_family; /* from ci_signature */
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uint32_t ci_model; /* from ci_signature */
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uint32_t ci_feat_val[5]; /* X86 CPUID feature bits
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* [0] basic features %edx
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* [1] basic features %ecx
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@ -660,7 +662,7 @@ cyrix6x86_cpu_setup(struct cpu_info *ci)
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void
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winchip_cpu_setup(struct cpu_info *ci)
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{
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switch (CPUID2MODEL(ci->ci_signature)) { /* model */
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switch (ci->ci_model) {
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case 4: /* WinChip C6 */
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disable_tsc(ci);
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}
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@ -725,7 +727,6 @@ identifycpu_cpuids(struct cpu_info *ci)
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static void
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via_cpu_probe(struct cpu_info *ci)
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{
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u_int model = CPUID2MODEL(ci->ci_signature);
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u_int stepping = CPUID2STEPPING(ci->ci_signature);
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u_int descs[4];
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u_int lfunc;
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@ -744,7 +745,7 @@ via_cpu_probe(struct cpu_info *ci)
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ci->ci_feat_val[2] |= descs[3];
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}
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if (model < 0x9 || (model == 0x9 && stepping < 3))
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if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3))
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return;
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/* Nehemiah or Esther */
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@ -761,11 +762,10 @@ via_cpu_probe(struct cpu_info *ci)
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static const char *
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intel_family6_name(struct cpu_info *ci)
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{
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int model = CPUID2MODEL(ci->ci_signature);
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const char *ret = NULL;
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u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize;
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if (model == 5) {
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if (ci->ci_model == 5) {
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switch (l2cache) {
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case 0:
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case 128 * 1024:
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@ -782,14 +782,14 @@ intel_family6_name(struct cpu_info *ci)
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ret = "Pentium II Xeon";
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break;
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}
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} else if (model == 6) {
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} else if (ci->ci_model == 6) {
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switch (l2cache) {
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case 256 * 1024:
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case 512 * 1024:
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ret = "Mobile Pentium II";
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break;
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}
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} else if (model == 7) {
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} else if (ci->ci_model == 7) {
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switch (l2cache) {
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case 512 * 1024:
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ret = "Pentium III";
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@ -799,7 +799,7 @@ intel_family6_name(struct cpu_info *ci)
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ret = "Pentium III Xeon";
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break;
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}
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} else if (model >= 8) {
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} else if (ci->ci_model >= 8) {
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if (ci->ci_brand_id && ci->ci_brand_id < 0x10) {
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switch (ci->ci_brand_id) {
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case 0x3:
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@ -836,150 +836,87 @@ intel_family6_name(struct cpu_info *ci)
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* "Revision Guide for AMD NPT Family 0Fh Processors"
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* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
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* and other miscellaneous reports.
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*
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* This is all rather pointless, these are cross 'brand' since the raw
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* silicon is shared.
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*/
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static const char *
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amd_amd64_name(struct cpu_info *ci)
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{
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int extfamily, extmodel, model;
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const char *ret = NULL;
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static char family_str[32];
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model = CPUID2MODEL(ci->ci_signature);
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extfamily = CPUID2EXTFAMILY(ci->ci_signature);
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extmodel = CPUID2EXTMODEL(ci->ci_signature);
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/* Only called if family >= 15 */
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switch (extfamily) {
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case 0x00:
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switch (model) {
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case 0x1:
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switch (extmodel) {
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case 0x2: /* rev JH-E1/E6 */
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case 0x4: /* rev JH-F2 */
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ret = "Dual-Core Opteron";
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break;
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}
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break;
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case 0x3:
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switch (extmodel) {
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case 0x2: /* rev JH-E6 (Toledo) */
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ret = "Dual-Core Opteron or Athlon 64 X2";
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break;
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case 0x4: /* rev JH-F2 (Windsor) */
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ret = "Athlon 64 FX or Athlon 64 X2";
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break;
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}
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break;
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case 0x4:
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switch (extmodel) {
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case 0x0: /* rev SH-B0/C0/CG (ClawHammer) */
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case 0x1: /* rev SH-D0 */
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ret = "Athlon 64";
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break;
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case 0x2: /* rev SH-E5 (Lancaster?) */
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ret = "Mobile Athlon 64 or Turion 64";
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break;
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}
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break;
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case 0x5:
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switch (extmodel) {
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case 0x0: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */
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ret = "Opteron or Athlon 64 FX";
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break;
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case 0x1: /* rev SH-D0 */
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case 0x2: /* rev SH-E4 */
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ret = "Opteron";
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break;
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}
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break;
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case 0x7:
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switch (extmodel) {
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case 0x0: /* rev SH-CG (ClawHammer) */
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case 0x1: /* rev SH-D0 */
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ret = "Athlon 64";
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break;
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case 0x2: /* rev DH-E4, SH-E4 */
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ret = "Athlon 64 or Athlon 64 FX or Opteron";
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break;
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}
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break;
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case 0x8:
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switch (extmodel) {
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case 0x0: /* rev CH-CG */
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case 0x1: /* rev CH-D0 */
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ret = "Athlon 64 or Sempron";
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break;
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case 0x4: /* rev BH-F2 */
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ret = "Turion 64 X2";
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break;
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}
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break;
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case 0xb:
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switch (extmodel) {
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case 0x0: /* rev CH-CG */
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case 0x1: /* rev CH-D0 */
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ret = "Athlon 64";
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break;
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case 0x2: /* rev BH-E4 (Manchester) */
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case 0x4: /* rev BH-F2 (Windsor) */
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ret = "Athlon 64 X2";
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break;
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case 0x6: /* rev BH-G1 (Brisbane) */
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ret = "Athlon X2 or Athlon 64 X2";
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break;
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}
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break;
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case 0xc:
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switch (extmodel) {
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case 0x0: /* rev DH-CG (Newcastle) */
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case 0x1: /* rev DH-D0 (Winchester) */
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case 0x2: /* rev DH-E3/E6 */
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ret = "Athlon 64 or Sempron";
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break;
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}
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break;
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case 0xe:
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switch (extmodel) {
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case 0x0: /* rev DH-CG (Newcastle?) */
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ret = "Athlon 64 or Sempron";
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break;
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}
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break;
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case 0xf:
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switch (extmodel) {
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case 0x0: /* rev DH-CG (Newcastle/Paris) */
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case 0x1: /* rev DH-D0 (Winchester/Victoria) */
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case 0x2: /* rev DH-E3/E6 (Venice/Palermo) */
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case 0x4: /* rev DH-F2 (Orleans/Manila) */
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case 0x5: /* rev DH-F2 (Orleans/Manila) */
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case 0x6: /* rev DH-G1 */
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ret = "Athlon 64 or Sempron";
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break;
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}
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break;
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switch (ci->ci_family) {
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case 15:
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switch (ci->ci_model) {
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case 0x21: /* rev JH-E1/E6 */
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case 0x41: /* rev JH-F2 */
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return "Dual-Core Opteron";
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case 0x23: /* rev JH-E6 (Toledo) */
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return "Dual-Core Opteron or Athlon 64 X2";
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case 0x43: /* rev JH-F2 (Windsor) */
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return "Athlon 64 FX or Athlon 64 X2";
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case 0x24: /* rev SH-E5 (Lancaster?) */
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return "Mobile Athlon 64 or Turion 64";
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case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */
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return "Opteron or Athlon 64 FX";
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case 0x15: /* rev SH-D0 */
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case 0x25: /* rev SH-E4 */
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return "Opteron";
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case 0x27: /* rev DH-E4, SH-E4 */
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return "Athlon 64 or Athlon 64 FX or Opteron";
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case 0x48: /* rev BH-F2 */
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return "Turion 64 X2";
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case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */
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case 0x07: /* rev SH-CG (ClawHammer) */
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case 0x0b: /* rev CH-CG */
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case 0x14: /* rev SH-D0 */
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case 0x17: /* rev SH-D0 */
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case 0x1b: /* rev CH-D0 */
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return "Athlon 64";
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case 0x2b: /* rev BH-E4 (Manchester) */
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case 0x4b: /* rev BH-F2 (Windsor) */
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return "Athlon 64 X2";
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case 0x6b: /* rev BH-G1 (Brisbane) */
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return "Athlon X2 or Athlon 64 X2";
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case 0x08: /* rev CH-CG */
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case 0x0c: /* rev DH-CG (Newcastle) */
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case 0x0e: /* rev DH-CG (Newcastle?) */
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case 0x0f: /* rev DH-CG (Newcastle/Paris) */
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case 0x18: /* rev CH-D0 */
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case 0x1c: /* rev DH-D0 (Winchester) */
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case 0x1f: /* rev DH-D0 (Winchester/Victoria) */
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case 0x2c: /* rev DH-E3/E6 */
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case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */
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case 0x4f: /* rev DH-F2 (Orleans/Manila) */
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case 0x5f: /* rev DH-F2 (Orleans/Manila) */
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case 0x6f: /* rev DH-G1 */
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return "Athlon 64 or Sempron";
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default:
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ret = "Unknown AMD64 CPU";
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break;
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}
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break;
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case 0x01:
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ret = "Family 10h";
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break;
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case 0x02:
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ret = "Family 11h";
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break;
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case 0x03:
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ret = "Family 12h";
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break;
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case 0x05:
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ret = "Family 14h";
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break;
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case 0x06:
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ret = "Family 15h";
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break;
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return "Unknown AMD64 CPU";
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#if 0
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case 16:
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return "Family 10h";
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case 17:
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return "Family 11h";
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case 18:
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return "Family 12h";
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case 19:
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return "Family 14h";
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case 20:
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return "Family 15h";
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#endif
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default:
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ret = "Unknown AMD64 CPU";
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break;
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}
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return ret;
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snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family);
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return family_str;
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}
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static void
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@ -989,7 +926,6 @@ cpu_probe_base_features(struct cpu_info *ci, const char *cpuname)
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u_int descs[4];
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int iterations, i, j;
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uint8_t desc;
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uint32_t miscbytes;
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uint32_t brand[12];
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memset(ci, 0, sizeof(*ci));
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@ -1025,13 +961,22 @@ cpu_probe_base_features(struct cpu_info *ci, const char *cpuname)
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x86_cpuid(1, descs);
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ci->ci_signature = descs[0];
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miscbytes = descs[1];
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/* Extract full family/model values */
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ci->ci_family = CPUID2FAMILY(ci->ci_signature);
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ci->ci_model = CPUID2MODEL(ci->ci_signature);
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if (ci->ci_family == 15)
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ci->ci_family += CPUID2EXTFAMILY(ci->ci_signature);
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if (ci->ci_family == 6 || ci->ci_family == 15)
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ci->ci_model += CPUID2EXTMODEL(ci->ci_signature) << 4;
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/* Brand is low order 8 bits of ebx */
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ci->ci_brand_id = descs[1] & 0xff;
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ci->ci_initapicid = (descs[1] >> 24) & 0xff;
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ci->ci_feat_val[1] = descs[2];
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ci->ci_feat_val[0] = descs[3];
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/* Brand is low order 8 bits of ebx */
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ci->ci_brand_id = miscbytes & 0xff;
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ci->ci_initapicid = (miscbytes >> 24) & 0xff;
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if (ci->ci_cpuid_level < 2)
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return;
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@ -1081,13 +1026,12 @@ static void
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cpu_probe_features(struct cpu_info *ci)
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{
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const struct cpu_cpuid_nameclass *cpup = NULL;
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int i, xmax, family;
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unsigned int i;
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if (ci->ci_cpuid_level < 1)
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return;
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xmax = __arraycount(i386_cpuid_cpus);
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for (i = 0; i < xmax; i++) {
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for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) {
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if (!strncmp((char *)ci->ci_vendor,
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i386_cpuid_cpus[i].cpu_id, 12)) {
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cpup = &i386_cpuid_cpus[i];
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@ -1098,12 +1042,10 @@ cpu_probe_features(struct cpu_info *ci)
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if (cpup == NULL)
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return;
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family = (ci->ci_signature >> 8) & 0xf;
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i = ci->ci_family - CPU_MINFAMILY;
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if (family > CPU_MAXFAMILY) {
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family = CPU_MAXFAMILY;
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}
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i = family - CPU_MINFAMILY;
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if (i >= __arraycount(cpup->cpu_family))
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i = __arraycount(cpup->cpu_family) - 1;
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if (cpup->cpu_family[i].cpu_probe == NULL)
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return;
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@ -1161,7 +1103,7 @@ static void
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amd_family5_setup(struct cpu_info *ci)
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{
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switch (CPUID2MODEL(ci->ci_signature)) {
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switch (ci->ci_model) {
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case 0: /* AMD-K5 Model 0 */
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/*
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* According to the AMD Processor Recognition App Note,
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@ -1242,7 +1184,8 @@ void
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identifycpu(int fd, const char *cpuname)
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{
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const char *name = "", *modifier, *vendorname, *brand = "";
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int class = CPUCLASS_386, i, xmax;
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int class = CPUCLASS_386;
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unsigned int i;
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int modif, family, model, ext_model;
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const struct cpu_extend_nameclass *modlist;
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const struct cpu_cpuid_nameclass *cpup = NULL;
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@ -1272,7 +1215,6 @@ identifycpu(int fd, const char *cpuname)
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ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info;
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modifier = "";
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} else {
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xmax = __arraycount(i386_cpuid_cpus);
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modif = (ci->ci_signature >> 12) & 0x3;
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family = CPUID2FAMILY(ci->ci_signature);
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if (family < CPU_MINFAMILY)
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@ -1280,7 +1222,7 @@ identifycpu(int fd, const char *cpuname)
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model = CPUID2MODEL(ci->ci_signature);
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ext_model = CPUID2EXTMODEL(ci->ci_signature);
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for (i = 0; i < xmax; i++) {
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for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) {
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if (!strncmp((char *)ci->ci_vendor,
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i386_cpuid_cpus[i].cpu_id, 12)) {
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cpup = &i386_cpuid_cpus[i];
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@ -1661,27 +1603,15 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
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{
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const struct x86_cache_info *cp;
|
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struct x86_cache_info *cai;
|
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int family, model;
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u_int descs[4];
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u_int lfunc;
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family = (ci->ci_signature >> 8) & 15;
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model = CPUID2MODEL(ci->ci_signature);
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/*
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* K5 model 0 has none of this info.
|
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*/
|
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if (family == 5 && model == 0)
|
||||
if (ci->ci_family == 5 && ci->ci_model == 0)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Get extended values for K8 and up.
|
||||
*/
|
||||
if (family == 0xf) {
|
||||
family += CPUID2EXTFAMILY(ci->ci_signature);
|
||||
model += CPUID2EXTMODEL(ci->ci_signature);
|
||||
}
|
||||
|
||||
/*
|
||||
* Determine the largest extended function value.
|
||||
*/
|
||||
|
|
@ -1701,7 +1631,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
|
|||
/*
|
||||
* K6-III and higher have large page TLBs.
|
||||
*/
|
||||
if ((family == 5 && model >= 9) || family >= 6) {
|
||||
if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) {
|
||||
cai = &ci->ci_cinfo[CAI_ITLB2];
|
||||
cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]);
|
||||
cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]);
|
||||
|
|
@ -1802,7 +1732,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
|
|||
/*
|
||||
* Determine L3 cache info on AMD Family 10h and newer processors
|
||||
*/
|
||||
if (family >= 0x10) {
|
||||
if (ci->ci_family >= 0x10) {
|
||||
cai = &ci->ci_cinfo[CAI_L3CACHE];
|
||||
cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]);
|
||||
cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]);
|
||||
|
|
@ -1875,12 +1805,10 @@ static void
|
|||
via_cpu_cacheinfo(struct cpu_info *ci)
|
||||
{
|
||||
struct x86_cache_info *cai;
|
||||
int family, model, stepping;
|
||||
int stepping;
|
||||
u_int descs[4];
|
||||
u_int lfunc;
|
||||
|
||||
family = (ci->ci_signature >> 8) & 15;
|
||||
model = CPUID2MODEL(ci->ci_signature);
|
||||
stepping = CPUID2STEPPING(ci->ci_signature);
|
||||
|
||||
/*
|
||||
|
|
@ -1913,7 +1841,7 @@ via_cpu_cacheinfo(struct cpu_info *ci)
|
|||
cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]);
|
||||
cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]);
|
||||
cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]);
|
||||
if (model == 9 && stepping == 8) {
|
||||
if (ci->ci_model == 9 && stepping == 8) {
|
||||
/* Erratum: stepping 8 reports 4 when it should be 2 */
|
||||
cai->cai_associativity = 2;
|
||||
}
|
||||
|
|
@ -1922,7 +1850,7 @@ via_cpu_cacheinfo(struct cpu_info *ci)
|
|||
cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]);
|
||||
cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]);
|
||||
cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]);
|
||||
if (model == 9 && stepping == 8) {
|
||||
if (ci->ci_model == 9 && stepping == 8) {
|
||||
/* Erratum: stepping 8 reports 4 when it should be 2 */
|
||||
cai->cai_associativity = 2;
|
||||
}
|
||||
|
|
@ -1938,7 +1866,7 @@ via_cpu_cacheinfo(struct cpu_info *ci)
|
|||
x86_cpuid(0x80000006, descs);
|
||||
|
||||
cai = &ci->ci_cinfo[CAI_L2CACHE];
|
||||
if (model >= 9) {
|
||||
if (ci->ci_model >= 9) {
|
||||
cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]);
|
||||
cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]);
|
||||
cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]);
|
||||
|
|
|
|||
Loading…
Reference in New Issue