Complete support for FPU_VFP.
fpregs now contains vfpreg.
XXX vfpreg only has space for 16 64-bit FP registers though VFPv3 and later
have 32 64-bit FP registers.
but add a second argument to it to indicate whether the TLB/caches need to be
flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).
With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7
Add emulation of instruction which save/restore the VFP FPSCR.
Add a sysarch hook to VFP FPSCR manipulation.
[The emulation will be used by libc to store/fetch exception modes and
rounding mode on a per-thread basis.]
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well. Use .arch armv7a to get us the isb/dsb
instructions.
Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.
This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.
TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.
NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
from doc/BRANCHES:
idle lwp, and some changes depending on it.
1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.
identify_arm_cpu() prints out a helpful message when it detects that you're
trying to run on a CPU that you didn't configure for. Unfortunately, the
check for class_option being NULL is backward, so it either won't print the
class_option, or it will try to dereference a NULL. The patch just flips the
!= NULL to be == NULL.
kernel config option CPU_XSCALE_PXA2X0 is now obsoleted by
CPU_XSCALE_PXA250 and CPU_XSCALE_PXA270. If both of them are defined,
CPU is determined run-time.
This code takes no advantage of any 'new' features provided by
architecture 6 devices (such as physically tagged caches or new
MMU features), and basically runs the chip in a 'legacy v5' mode.
backed by physical pages (ie. because it reused a previously-freed one),
so that we can skip a bunch of useless work in that case.
this fixes the underlying problem behind PR 18543, and also speeds up fork()
quite a bit (eg. 7% on my pc, 1% on my ultra2) when we get a cache hit.
in question, whereas the ARM code was using it to hold the model
identification. To fix this, rename:
ci_cpuid -> ci_arm_cpuid
ci_cputype -> ci_arm_cputype (for consistency)
ci_cpurev -> ci_arm_cpurev (ditto)
ci_cpunum -> ci_cpuid
This makes top(1) give correct CPU numbers in its "STATE" column (all 0 for
now).
